—
18
—
SA
T-W
60
+ 3 _ 3 V
+ 3 _ 3 V
+ 3 _ 3 V
8 0 5
C E R M
5 0 V
2 0 %
0.1UF
C 0 2 1 4
TP_75
TP0205
TH
TP_75
TP0204
TH
TP_75
TP0202
TH
TP_75
TP0203
TH
+ 5 V
R 0 2 0 6
5 %
6 0 3
1 0 K
R 0 2 0 4
5 %
6 0 3
1 0 K
R 0 2 0 3
5 %
6 0 3
1 0 K
R 0 2 1 8
5 %
6 0 3
4.7K
R 0 2 1 7
5 %
6 0 3
4.7K
R 0 2 1 6
5 %
6 0 3
4.7K
R 0 2 1 3
5 %
6 0 3
1 0 K
R 0 2 1 2
5 %
6 0 3
1 0 K
R0211
5 %
6 0 3
1 0 K
R 0 2 1 0
5 %
6 0 3
1 0 K
R 0 2 1 9
5 %
6 0 3
4.7K
+ 3 _ 3 V
TP_75
TP0207
TH
TP_75
TP0206
TH
+ 3 _ 3 V
L 0 2 0 2
B K 2 1 2 5 H S 6 0 1
S M
L 0 2 0 3
B K 2 1 2 5 H S 6 0 1
S M
8 0 5
C E R M
5 0 V
2 0 %
0.1UF
C 0 2 2 4
R 0 2 2 8
5 %
6 0 3
1K
+ 3 _ 3 V
R 0 2 2 9
TK
5 % 1/16W
6 0 3
1 0 M
+ 5 V
R 0 2 4 0
5 %
6 0 3
1 0 K
R 0 2 2 0
5 %
6 0 3
1 0 K
R 0 2 2 2
5 %
6 0 3
1 0 K
R 0 2 2 3
5 %
6 0 3
1 0 K
R 0 2 2 4
5 %
6 0 3
1 0 K
R 0 2 2 5
5 %
6 0 3
1 0 K
R 0 2 2 7
5 %
6 0 3
1 0 K
R 0 2 2 6
5 %
6 0 3
1 0 K
R 0 2 8 1
5 %
6 0 3
1 0 K
R 0 2 8 0
5 %
6 0 3
1 0 K
R 0 2 3 0
5 %
6 0 3
1 0 K
R 0 2 3 1
5 %
6 0 3
1 0 K
R 0 2 3 2
5 %
6 0 3
1 0 K
R 0 2 3 3
5 %
6 0 3
1 0 K
6 0 3
5 %
0
R 0 2 9 9
R 0 2 3 8
5 %
6 0 3
1 0 K
R 0 2 3 7
5 %
6 0 3
1 0 K
R 0 2 6 1
5 %
6 0 3
1 0 K
1210
C E R M
10V
2 0 %
1 0 U F
C 0 2 2 5
R 0 2 6 2
5 %
6 0 3
4 7
R 0 2 8 2
5 %
6 0 3
4 7
6 0 3
1 %
1.62K
R 0 2 9 8
6 0 3
1 %
2 K
R 0 2 9 7
R 0 2 3 6
5 %
6 0 3
4.7K
R 0 2 3 5
5 %
6 0 3
2.2K
R 0 2 2 1
1 %
6 0 3
5.62K
A U D _ C L K
AUD_SDATAIN
C P U _ E V A L O _ N
C P U _ E W R R D Y _ N
C P U _ M O D E C L K
C P U _ V A L O _ N
D A C _ C O M P V B S
D A C _ C R C B V B S
D A C _ V R E F
D A C _ Y V B S
DIV_LLC
IR_IN
M O D _ C L K
M O D _ S D A T A I N
P L L _ B Y P A S S
P O T _ C L K
P P _ A C K _ N
P P _ B U S Y
P P _ E R R O R
P P _ F A U L T _ N
P P _ S E L E C T
RIO_DEVIORDY
RIO_DINT<7..0>
RIO_DRQ<1..0>
SYS_2XCLKIN
S Y S _ D P W R O K
S Y S _ P W R O K
S Y S _ R S W T C H _ N
TEST_MODE<3..0>
T E S T _ S C A N E N
AUD_BITCLK
A U D _ L R C L K
A U D _ S D A T A
C P U _ C R E S E T _ N
CPU_EVALI_N
CPU_INT_N
C P U _ M O D E I N
C P U _ S R E S E T _ N
CPU_VALI_N
C P U _ V C C O K
C P U _ W R R D Y _ N
D A C _ A P V D 0
D A C _ A P V D 1
D A C _ C O M P A O U T
D A C _ C O M P A P V S
D A C _ C R C B A O U T
D A C _ C R C B A P V S
D A C _ Y A O U T
D A C _ Y A P V S
M C 0 _ A D D R < 1 0 . . 0 >
M C 0 _ B S
M C 0 _ C A S _ N
M C 0 _ C K E
M C 0 _ C S _ N < 1 . . 0 >
M C 0 _ D Q M < 3 . . 0 >
M C 0 _ R A S _ N
M C 0 _ W E _ N
M C 1 _ A D D R < 1 0 . . 0 >
M C 1 _ B S
M C 1 _ C A S _ N
M C 1 _ C K E
M C 1 _ C S _ N < 1 . . 0 >
M C 1 _ D Q M < 3 . . 0 >
M C 1 _ R A S _ N
M C 1 _ W E _ N
MISC_LED<2..0>
MOD_BITCLK
M O D _ L R C L K
M O D _ S D A T A
PLL_LP
P L L _ M P O
PP_DIR
PP_INIT_N
RIO_DAK_N<1..0>
RIO_DEN_N<7..0>
R I O _ O E _ N
R I O _ W E _ N
S P D _ S D A T A
S Y S _ 5 V R S T _ N
S Y S _ R E S E T _ N
CPU_AD<31..0>
C P U _ C M D < 6 . . 0 >
DIV_BCLK
DIV_DATA<7..0>
DIV_HS
DIV_LRCLK
DIV_SDATA
DIV_VS
GPIO<19..0>
ID_DATA
IIC_CLK
IIC_DATA
IR_CLK
IR_OUT
MC0_DATA<31..0>
MC1_DATA<31..0>
P P _ A U T O F D _ N
PP_DATA<7..0>
PP_SELIN_N
P P _ S T R O B E _ N
RIO_ADDR<21..0>
RIO_CE_N<3..0>
RIO_DATA<15..0>
S M C _ C L K
S M C _ D A T A
SMC_FIT
S M C _ I N S E R T _ N
S M C _ P E N _ N
S M C _ R E S E T _ N
U A R T _ C T S _ N
U A R T _ D C D _ N
U A R T _ D T R _ N
U A R T _ R T S _ N
U A R T _ R X D
U A R T _ T X D
VID_DATA<7..0>
V I D _ H S Y N C _ N
VID_VSYNC_N
P L L _ A G D
PLL_VAA
VDD<28..0>
VDD3<16..0>
VSS<36..0>
VSS2<28..0>
VSS3<16..0>
DAC_NC<1..0>
P L L _ D G N
P L L _ D V D
$Id: solo.mpl,v 1.30 1997/05/21 10:31:53 lyang Exp $
2 2 0 P F
5 %
C 0 2 1 7
C E R M
5 0 V
2 2 0 P F
5 %
C 0 2 1 6
C E R M
5 0 V
2 2 0 P F
5 %
C 0 2 1 5
C E R M
5 0 V
8 0 5
C E R M
5 0 V
2 0 %
0.1UF
C 0 2 1 3
1210
C E R M
16V
2 0 %
1 0 U F
C 0 2 1 9
D R A W I N G
LAST_MODIFIED=Mon Apr 10 12:33:20 2000
C WEBTV NETWORKS, INC. 1999
representative of a named recipient.
or otherwise use this document unless you are an authorized
than the recipient is not authorized. You may not read, copy,
information. Disclosure of this information to anyone other
This document contains privileged or otherwise legally protected
APPROVED:
BLOCK:
SET:
ENGINEER:
of
SET
B L O C K
REVISION:
PAGE:
of
REVISION:
PAGE:
D
C
B
A
1
2
3
4
D
5
6
7
8
C
B
A
1
2
3
4
5
6
7
8
DATE:
1
2
3 7
4
PVT
E L M E R
S O L O 2
SLEATOR/FULLER
0.0
R E M O V E D R 0 2 0 9
R E M O V E D R 0 2 0 7
R E M O V E D R 0 2 0 2
750 PS DELAY: ~4.5 INCH
SERPENTINE LENGTH FOR
N C
WHILE MAKING IT EASY TO CONNECT
THESE PINS WILL BE NAMED VDD2
VDD3 = INPUT BUFFER POWERS (IN SOLO2.5,
V S S 2 = C O R E L O G I C G R O U N D S
V S S = O U T P U T B U F F E R G R O U N D S
V S S 3 = I N P U T B U F F E R G R O U N D S
V D D = C O R E L O G I C A N D O U T P U T B U F F E R P O W E R S
SOLO2 POWER PARTITIONS
AND WILL BECOME CORE LOGIC POWERS)
F S W
C S Y N C
FUD TO THE CPU
PRESERVES HISTORIC SIGNAL FLOW
R E M O V E D R 0 2 0 0
R E M O V E D R 0 2 0 1
R E M O V E D R 0 2 0 5
R E M O V E D R 0 2 0 8
R E M O V E D R 0 2 1 4
R E M O V E D R 0 2 1 5
NOTES:
PRESERVES HISTORIC SIGNAL FLOW
VID_VDD
D A C _ C O M P V B S
D A C _ C R C B V B S
RIO_DINT<7..0>\I
T E S T _ S C A N E N
SYS_2XCLKIN\I
RIO_DRQ<0>\I
SYS_5VRESET_N\I
MOD_SDATAIN\I
SOLO_VDD \R 17
RIO_DRQ<1..0>\I
AUD_CLK\I
AUD_SDATAIN\I
D A C _ C O M P V B S
D A C _ C R C B V B S
D A C _ V R E F
D A C _ Y V B S
DIV_LLC\I
IR_IN\I
MOD_CLK\I
MOD_SDATAIN\I
P L L _ B Y P A S S
POT_CLK\I
PP_ACK_N\I
PP_BUSY\I
PP_ERROR\I
PP_FAULT_N\I
PP_SELECT\I
RIO_DEVIORDY\I
RIO_DINT<7..0>\I
SYS_DPWROK\I
SYS_PWROK\I
SYS_RSWTCH_N\I
TEST_MODE<3..0>
P L L _ A G D
PLL_VAA
SOLO_VSS \R 37
SOLO_VSS \R 29
SOLO_VSS \R 17
P L L _ D G N
P L L _ D V D
SYS_RESET_N\I
RIO_DEVIORDY\I
P L L _ B Y P A S S
IIC_DATA\I
IIC_CLK\I
D A C _ Y V B S
CMD_TWIZZLE<6..0>
CPU_CMD<8..0>\I
SOLO_VDD \R 29
CPU_VALOUT_N\I
CPU_EVALO_N\I
C P U _ M O D E C L K \ I
C P U _ E W R R D Y _ N \ I
S O L O _ V S S
RIO_DRQ<1>\I
TEST_MODE<3..0>
MOD_CLK\I
SYS_5VRESET_N\I
SYS_RESET_N\I
P L L _ D G N
P L L _ D V D
GPIO<19..0>\I
AUD_BITCLK\I
AUD_LRCLK\I
AUD_SDATA\I
CPU_CRESET_N\I
CPU_EVALI_N\I
CPU_INT_N\I
CPU_MODEIN\I
CPU_SRESET_N\I
CPU_VALIN_N\I
CPU_VCCOK\I
C P U _ W R R D Y _ N \ I
VID_VDD
VID_VDD
DAC_COMPAOUT\I
VID_VSS
DAC_CRCBAOUT\I
VID_VSS
DAC_YAOUT\I
VID_VSS
MC0_ADDR<10..0>\I
MC0_BS\I
MC0_CAS_N\I
MC0_CKE\I
MC0_CS_N<1..0>\I
MC0_DQM<3..0>\I
MC0_RAS_N\I
MC0_WE_N\I
MC1_ADDR<10..0>\I
MC1_BS\I
MC1_CAS_N\I
MC1_CKE\I
MC1_CS_N<1..0>\I
MC1_DQM<3..0>\I
MC1_RAS_N\I
MC1_WE_N\I
MISC_LED<2..0>\I
MOD_BITCLK\I
MOD_LRCLK\I
MOD_SDATA\I
PLL_LP
P L L _ M P O
PP_DIR\I
PP_INIT_N\I
RIO_DAK_N<1..0>\I
RIO_DEN_N<7..0>\I
RIO_OE_N\I
RIO_WE_N\I
SPD_SDATA\I
CPU_AD<31..0>\I
CMD_TWIZZLE<6..0>
DIV_BCLK\I
DIV_DATA<7..0>\I
DIV_HS\I
DIV_LRCLK\I
DIV_SDATA\I
DIV_VS\I
GPIO<19..0>\I
ID_DATA\I
IIC_CLK\I
IIC_DATA\I
IR_CLK\I
IR_OUT\I
MC0_DATA<31..0>\I
MC1_DATA<31..0>\I
PP_AUTOFD_N\I
PP_DATA<7..0>\I
PP_SELIN_N\I
PP_STROBE_N\I
RIO_ADDR<21..0>\I
RIO_CE_N<3..0>\I
RIO_DATA<15..0>\I
SMC_CLK\I
SMC_DATA\I
SMC_FIT\I
SMC_INSERT_N\I
SMC_PEN_N\I
SMC_RESET_N\I
UART_CTS_N\I
UART_DCD_N\I
UART_DTR_N\I
UART_RTS_N\I
UART_RXD\I
UART_TXD\I
VID_DATA<7..0>\I
VID_HSYNC_N\I
VID_VSYNC_N\I
DIV_BCLK\I
AUD_BITCLK\I
DIV_SDATA\I
AUD_SDATA\I
DIV_LRCLK\I
AUD_LRCLK\I
VID_VDD
D A C _ V R E F
VID_VSS
A B B R E V = B S L 2
TITLE=BLK_SOLO2
E M P T Y
E M P T Y
U 0 2 0 1
C11
C12
B11
B12
A11
U 3
F1
J4
H 4
R 2
J3
Y2
V1
W 1
Y4
R 3
H 3
A4
B 4
C 7
F9
D 9
E9
B 5
B 6
C 6
A5
C 8
A6
F3
F2
B 2
G 2
G 4
E3
AC4
A2
A3
R 2 5
R 2 6
A19
AD10
AD9
AD13
AE9
AD8
AF24
AC23
AA25
AE24
AD23
A21
B 2 0
C21
B21
A20
AB2
AA3
AB1
Y3
V5
AC1
V6
D12
A16
C15
B16
A17
C16
D15
A15
B17
D16
B15
A26
C 2 4
B 2 5
AC3
AF3
AF1
AD3
AD2
AE1
A12
AC2
AE2
AA2
AA1
A1
B 3
E11
D17
C18
A18
B18
D18
C17
A9
A8
P A D S _ O N L Y
B G A
E M P T Y
E M P T Y
3
2
1
E M P T Y
19
18
17
16
13
12
11
10
3
4
6
7
6
5
4
0
1
2
3
3
2
1
0
0
1
3
5
6
7
8
0
1
2
3
4
5
6
Summary of Contents for DIRECTV RECEIVER SAT-W60
Page 52: ... 52 SAT W60 POWER SUPPLY ...
Page 59: ...SAT W60 ...