122
DVP-CX777ES
Pin No.
Pin Name
I/O
Description
61
VDD
—
Power supply terminal (+3.3V)
62
VSS
—
Ground terminal
63
DLDRI
I
Audio data input from the audio DSP
64
CSWI
I
Audio data (for center and woofer) input from the audio DSP
65
SLSRI
I
Audio data (for rear) input from the audio DSP
66
FLFRI
I
Audio data (for front) input from the audio DSP
67
TEST3
I
Input terminal for the test
68
CLK512
I
Master clock (27 MHz) input from the clock generator
69
VSS
—
Ground terminal
70
XRST
I
Reset signal input from the system controller “L”: reset
71
VDD
—
Power supply terminal (+3.3V)
72
SCLK
I
Serial clock signal input from the system controller
73
XCS
I
Chip select signal input from the mechanism controller
74
SI
I
Serial data input from the system controller
75
SO
O
Serial data output to the system controller
76
DEXRI
I
Not used
77
DMLI
I
DSD data input for L-ch down mix to the DSD decoder
78
DMRI
I
DSD data input for R-ch down mix to the DSD decoder
79
VSS
—
Ground terminal
80
PHAI
I
Clock signal input from DSD decoder
81
BCKAI
I
Bit clock signal input for DSD data output from DSD decoder
82
DQM
O
Not used
83
DLI
I
DSD data (for front L-ch) input from DSD decoder
84
DRI
O
DSD data (for front R-ch) input from DSD decoder
85
DCI
O
DSD data (for center) input from DSD decoder
86
DLFEI
O
DSD data (for woofer) input from DSD decoder
87
DLSI
O
DSD data (for rear L-ch) input from DSD decoder
88
DRSI
O
DSD data (for rear R-ch) input from DSD decoder
89
VSS
—
Ground terminal
90 to 95
D15 to D10
I/O
Two-way data bus with the SD-RAM
96
VDD
—
Power supply terminal (+3.3V)
97, 98
D9, D8
I/O
Two-way data bus with the SD-RAM
99
GND
—
Ground terminal
100
D0
I/O
Two-way data bus with the SD-RAM
