24
24
DVP-NW50
DVP-NW50
6-2. BLOCK DIAGRAM — MAIN (1) SECTION —
U16
DIGITAL AUDIO RECEIVER
U17
BUFFER
EGP1004
EGP1005
EGP1006
EGP1007
EG$RESET
EECLK
SPDIF$IN
EEDATA
DVD$CE
EECLK
EEDATA
DVD$CE
U8
BUFFER
U21
BUFFER
SCLK
MCLK
LRCK
SCLK
SDATA
TXD ARM
RXD_ARM
LRCK
MCLK
SDOUT
SDIN
U6
BUFFER
U27
BUFFER
D5
Q9
Q10
U18
BUFFER
VIDEO$Y
VIDEO$C
CVBS
U43
NOISE DETECT
U19
BUFFER
U23
BUFFER
VCXO_PWM
EGP1004
EGP1005
EGP1006
EGP1007
EG$RESET
VIDEO
S VIDEO
Q2
BUFFER
Q5,Q7
BUFFER
Q8
BUFFER
Q6
BUFFER
U34
PROTECTOR
U36
PROTECTOR
U35
PROTECTOR
VIDEO$Y
VIDEO$C
EP$S1_VIDEO
CVBS
J10
J16
4
2
3
1
X2
11.2896MHz
• SIGNAL PATH
: AUDIO(DIGITAL)
: CHROMA
: Y
: VIDEO