HAP-Z1ES
HAP-Z1ES
36
36
5-2. BLOCK DIAGRAM - AUDIO Section -
D/A CONVERTER
IC201
DATA
5
BCK
6
LRCK
4
FPGA
IC001 (2/2)
IO/DIFFIO_R2N D12
SCL
7
IOUTL+ 25
IOUTL– 26
IOUTR+ 17
IOUTR– 18
SWITCHING
IC101
COUNTER
IC102
IO/DIFFIO_R4P/DM0R E10
IO/DIFFIO_R2P D11
IO/DIFFIO_R14P/DQ0R K11
IO/DIFFIO_R13N/DQ0R L13
IO/DIFFIO_R9N/DQ0R J13
IO/RUP3 N13
IO/DIFFIO_R9P/DQ0R K13
CLK4/DIFFCLK_2N G13
IO/DIFFIO_R14N/DQ0R K12
MDI
11
MC
12
nMS
10
nRST
14
IO/RDN3 M13
X101
22.5792MHz
X102
24.576MHz
H10
IO/DQS1R/CQ0R#/DPCLK7
H12
IO/VREFB5N0
: AUDIO (DIGITAL)
SIGNAL PATH
: AUDIO (ANALOG)
D/A CONVERTER
IC251
DATA
5
BCK
6
LRCK
4
SCL
7
IOUTL+ 25
IOUTL– 26
IOUTR+ 17
IOUTR– 18
MDI
11
MC
12
nMS
10
nRST
14
CLOCK
BUFFER
IC103
LINE AMP
IC202
LOW-PASS
FILTER
IC203
LOW-PASS
FILTER
IC253
MIX AMP
IC204
ASDMUTE
>002B
RY201
RY202
RELAY DRIVE
Q152, 202
SWITCHING
IC107
-1
-2
LINE AMP
IC252
-1
-2
RY252
-1
-2
J201
CN202
UNBALANCED
LINE OUT
J251
R
L
BALANCED
LINE OUT
R
L
AMUTE
>001B
RELAY DRIVE
Q151, 201
2
3
1
CN252
2
3
1
(Page 35)
(Page 38)
Summary of Contents for HAP-Z1ES
Page 119: ...MEMO HAP Z1ES 119 ...