74
HCD-C5
I/O
Pin Name
Pin No.
Description
O
O
I/O
O
I/O
O
O
O
—
—
O
O
O
I
I
O
O
O
O
O
—
O
O
O
O
O
O
O
O
I
I
I
I
I
I
—
—
—
I
—
—
O
O
O
I
O
O
I
I
I
FL-DATA
FL-CLK
SDA
FL-CE
SCL
FL-RST
CXD-DATA
CXD-CLK
EVDD
EVSS
CXD-XLT
PWM1
LDON
SENSE
SUBQ
CHECK
SCLK
CTRL1
PWM2
PWM3
VPP
SP-MUTE
1-4
DMUTE
AMUTE
LODNEG
LODPOS
BDPWR
BDRST
SW1
SW2
SW3(ENC-A)
SW4(ENC-B)
RESET
XT1
XT2
REGC
X2
X1
VSS
VDD
CLKOUT
PLL-CLK
PLL-DO(
µ
COM-ST)
PLL-DI(ST-
µ
COM)
PLL-CE
ST-MUTE
STEREO
TUNED
RDS-DATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
FL tube data signal output
FL tube clock signal output
IIC data signal input or output
FL tube enable signal output
IIC clock signal input or output
FL tube reset signal output
Data signal output to DSP
Clock signal output to DSP
Power supply for I/O port
Ground for I/O port
Latch signal output to DSP
PWM1 signal output
Laser power control signal output
CD SENSE signal input
CD SUBQ signal input
Not used (open)
CD SUBQ clock signal output
CTRL1 (setting double speed) signal output
PWM2 signal output
PWM3 signal output
Not used
Not used (open)
Not used (open)
Muting signal output to DAC
Not used (open)
Loading motor control signal output
Loading motor control signal output
CD power control signal output
CD reset signal output
Loading switch signal input
Loading switch signal input
Loading switch signal input
Loading switch signal input
Systen reset input
Sub clock input
Sub clock output
Terminal for regulator clock
Main system clock output
Main system clock input
Ground
Power supply
Clock output (open)
Tuner clock signal output
Tuner data signal output
Tuner data signal input
Tuner chip enable signal output
Tuner muting signal output
Stereo tuning signal input
TUNED detect signal input
RDS data signal input
• IC501
µ
PD703032AYGF-M01-3BA MASTER CONTROL (UCOM BOARD)
