94
HCD-HDX500/HDX501W
Pin No.
Pin Name
I/O
Description
109
GND
-
Ground terminal
110
VDDINT
-
Power supply terminal (+1.2V) (for core)
111
GND
-
Ground terminal
112
VDDINT
-
Power supply terminal (+1.2V) (for core)
113
GND
-
Ground terminal
114
VDDINT
-
Power supply terminal (+1.2V) (for core)
115
GND
-
Ground terminal
116
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
117
GND
-
Ground terminal
118
VDDINT
-
Power supply terminal (+1.2V) (for core)
119
GND
-
Ground terminal
120
VDDINT
-
Power supply terminal (+1.2V) (for core)
121
RESET*
I
Reset signal input from the system controller "L": reset
122
SPIDS*
I
Device selection signal input from the system controller
123
GND
-
Ground terminal
124
VDDINT
-
Power supply terminal (+1.2V) (for core)
125
SPICLK
I
Serial data transfer clock signal input from the system controller
126
MISO
I/O
When DSP is master: Serial data input from the flash memory
When DSP is slave: Serial data output to the main system controller
127
MOSI
I/O
When DSP is master: Serial data output to the flash memory
When DSP is slave: Serial data input from the main system controller
128
GND
-
Ground terminal
129
VDDINT
-
Power supply terminal (+1.2V) (for core)
130
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
131
AVDD
-
Power supply terminal (+1.2V) (analog system)
132
AVSS
-
Ground terminal (analog system)
133
GND
-
Ground terminal
134
CLKOUT
O
Local clock signal output terminal Not used
135
EMU*
O
Emulation status signal output terminal Not used
136
TDO
O
Test data output terminal (for JTAG) Not used
Test data input terminal (for JTAG) Not used
Test reset signal input terminal (for JTAG) Not used
Test clock signal input terminal (for JTAG) Not used
Test mode select signal input terminal (for JTAG) Not used
System clock input terminal (25 MHz)
System clock output terminal (25 MHz)
Power supply terminal (+3.3V) (for I/O)
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