48
HCD-RG100
Pin No.
Pin Name
I/O
Description
97
XLAT
I
Latch input from CPU The serial data is latched at the falling edge
98
CLOCK
I
Serial data transfer clock input from CPU
99
VDD
–
Internal digital power supply
100
SENS
O
SENS output to CPU
101
SCLK
I
SENS serial data readout clock input
102
ATSK
I/O
Anti-shock input/output
103
WFCK
O
WFCK output (Not used)
104
XUGF
O
XUGF output (Not used)
105
XPCK
O
XPCK output (Not used)
106
GFS
O
GFS output (Not used)
107
C2PO
O
C2PO output (Not used)
108
SCOR
O
High output when the subcode sync, S0 or S1, is detected
109
VDD
–
Internal digital power supply
110
C4M
O
4 2336MHz output (Not used)
111
WDCK
O
Word clock output f = 2Fs (Not used)
112
COUT
I/O
Track number count signal input/output (Not used)
Summary of Contents for HCD-RG100
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