65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 to 34
35
36 to 40
41
42
43
44
45
46
47
48
49
50, 51
52
53
54
55
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
DIN0
DIN1
DOUT
DADTI
LRCKI
XBCKI
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03 to A00
A10
A04 to A08
A11
DVSS
XOE
XCAS
A09
XRAS
XWE
D1
D0
D2, D3
MVCI
ASYO
ASYI
AVDD
• IC151 CXD2662R Digital Signal Processor, Digital Servo Signal Processor (BD (MD) BOARD)
Function
Pin No.
Pin Name
I/O
O
O
O
O
I
I (S)
I (S)
O (3)
O (3)
I (S)
O
O
I
O
I
I
O
I
I
I
O
I
I
I
I
O
O
O
O
—
O
O
O
O
—
O
O
O
O
O
I/O
I/O
I/O
I (S)
O
I (A)
—
FOK signal output to the system control (monitor output)
“H” is output when focus is on
Track jump detection signal output to the system control (monitor output)
Monitor 2 output to the system control (monitor output)
Monitor 3 output to the system control (monitor output)
Writing data signal input from the system control
Serial clock signal input from the system control
Serial latch signal input from the system control
Reading data signal output to the system control
Internal status (SENSE) output to the system control
Reset signal input from the system control
“L”: Reset
Subcode Q sync (SCOR) output to the system control
“L” is output every 13.3 msec. Almost all, “H” is output
Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system control
Laser power switching input from the system control
“H”: Recording, “L”: Playback
Interrupt status output to the system control
Recording data output enable input from the system control
System clock input (512Fs=22.5792 MHz)
System clock output (512Fs=22.5792 MHz) (Not used)
System clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (Fixed at “H”)
Digital audio input (Optical input)
Digital audio input (Optical input)
Digital audio output (Optical output)
Serial data input
LR clock input
“H” : Lch, “L” : R ch
Serial data clock input
Data input from the A/D converter
Data output to the D/A converter
LR clock output for the A/D and D/A converter (44.1 kHz)
Bit clock output to the A/D and D/A converter (2.8224 MHz)
11.2896 MHz clock output (Not used)
+3V power supply (Digital)
DRAM address output
DRAM address output (Not used)
DRAM address output
DRAM address output (Not used)
Ground (Digital)
Output enable output for DRAM
CAS signal output for DRAM
Address output for DRAM
RAS signal output for DRAM
Write enable signal output for DRAM
Data input/output for DRAM
Clock input from an external VCO (Fixed at “L”)
Playback EFM duplex signal output
Playback EFM comparator slice level input
+3V power supply (Analog)
* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
Summary of Contents for HMC-NX5MD
Page 44: ...44 44 HMC NX5MD 6 3 SCHEMATIC DIAGRAM CD SECTION Page 50 PIN FUNCTION ...
Page 47: ...47 47 HMC NX5MD 6 6 SCHEMATIC DIAGRAM MD SECTION 1 2 48 48 48 PIN FUNCTION ...
Page 48: ...48 48 HMC NX5MD 6 7 SCHEMATIC DIAGRAM MD SECTION 2 2 47 47 47 52 52 PIN FUNCTION ...
Page 49: ...49 49 HMC NX5MD 6 8 SCHEMATIC DIAGRAM MAIN SECTION 1 2 Page 52 Page 50 Page 50 ...
Page 52: ...52 52 HMC NX5MD 6 11 SCHEMATIC DIAGRAM DIGITAL SECTION Page 48 Page 48 Page 49 PIN FUNCTION ...
Page 54: ...54 54 HMC NX5MD 6 13 SCHEMATIC DIAGRAM PANEL SECTION Page 50 ...
