3-4.
Circuit Description
3-4-1.
Recording System
Video input signals
• The composite analog video signal is input to CN203 on the DIF-222 board, and the S video signal is input to
CN204 on the DIF-222 board. These signals are buffered and are then input to the video decoder (IC301) in which
an input signal is selected, A/D converted, and decoded. The decoded data is sent through CN101 to the pixel
converter FPGA (IC001) on the HPR-50 board.
• The DVI-D digital video signal is input to CN202 on the DIF-222 board, and the HDMI digital video signal is input
to CN201 on the DIF-222 board, and these signals are input to the video decoder (IC301). In the same way as analog
signal, an input signal is selected, A/D converted, and decoded in the video decoder (IC301). The decoded data is
sent through CN101 to the pixel converter FPGA (IC001) on the HPR-50 board.
Audio input signals
• Analog audio signals are input from CN401 on the HPR-50 board, and are then A/D converted by IC004. The
converted data is input to the pixel converter FPGA (IC001).
• The HDMI audio signal is decoded in the video decoder (IC301) on the DIF-222 board, and is then converted to
the recording clock rate by the sample rate converter (IC302). Then this signal is sent through CN101 to the pixel
converter FPGA (IC001) on the HPR-50 board.
Recording operation
• The pixel converter FPGA (IC001) on the HPR-50 board selects an input video signal according to the menu setting,
performs necessary pixel conversion, and then outputs the selected video signal to the video output side.
Video signals whose pixel size has been converted as needed are output in the SMPTE-274M (1080), SMPTE-296M
(720), or ITU-R BT.656 (SD) format, and are then input to the Codec Chip (IC002).
Input video signals are encoded in the H.264 recording format according to the set conditions.
• Audio signals that are input to the pixel converter FPGA (IC001) on the HPR-50 board are selected according to
the menu setting, and the selected signal is input to the Codec Chip (IC002).
Input audio signals are encoded according to the set conditions.
• Encoded video and audio signals are compressed and multiplexed to be recording data, and are then sent back to
the pixel converter FPGA (IC001) on the HPR-50 board. The recording data is sent from IC001 through the PCIe
connector (CN101) to the MB board, and is then processed by the software and is recorded in each device.
3-4-2.
Playback System
Playback operation
• Playback data is read from the internal HDD and the read playback data is sent to the PCIe connector (CN101) on
the MB board, and is then input to the pixel converter FPGA (IC001) on the HPR-50 board.
Data is input to the Codec Chip (IC002) to be decoded.
• Video signals decoded by the Codec Chip (IC002) are output to the FPGA (IC001) on the HPR-50 board in the
format used during recording.
• Playback data of audio signals is also decoded by the Codec Chip (IC002), and the decoded data is input to the
FPGA (IC001).
Video output signals
• Pixel sizes of decoded video signals are converted for each output by the pixel converter FPGA (IC001) on the
HPR-50 board. (This pixel conversion is not made for systems in which pixel size is output as it is.)
• After pixel conversion, the DVI-D OUT signal is sent through CN223 to the DIF-223 board. This signal is converted
to the DVI-D format by the DVI-D encoder (IC202), and is then output to the DVI-D OUT connector (CN201) on
the rear panel.
HVO-500MD/HVO-550MD
3-5
