– 36 –
IC502
µ
PD753012AGK-781-BE9 (SUB SYSTEM CONTROL, LCD DRIVE)
Pin No.
Pin name
I/O
Description
1 – 18
S12 – S29
O
LCD segment signal output.
19, 20
–––––
–
Not used (OPEN).
21
COM0
O
LCD common signal output.
22
COM1
O
LCD common signal output.
23
COM2
O
LCD common signal output.
24
COM3
O
LCD common signal output.
25
BIAS
O
Bias output for LCD.
26
VLC0
–
LCD drive power supply.
27
VLC1
–
LCD drive power supply.
28
VLC2
–
LCD drive power supply.
29 – 37
–––––
–
Not used (Connect to GND).
38
REQ
I
Request signal input.
39
SCK
I
Sub clock input.
40
–––––
–
Not used (fix to “L”).
41
SI
I
Data signal input.
42 – 45
–––––
–
Not used (Connect to GND).
46
ACK
O
PLL clock signal control output.
47 – 53
–––––
–
Not used (OPEN).
54
VDD
–
Power supply terminal.
55
XT1
I
Sub clock input (32.768kHz).
56
XT2
O
Sub clock output (32.768kHz).
57
IC
–
Connect to VDD.
58
X1
I
System main clock input (4MHz).
59
X2
O
System main clock output (4MHz).
60 – 67
–––––
–
Not used (OPEN).
68 – 80
S0 – S11
O
LCD segment signal output.
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