PCS-G50/G50P
6-14
ENHANSED DMA CONTROLLER
(EDMA)
EMIF A
TIMER 2
TIMER 1
TIMER 0
PCI-66
EMAC
MDIO
BOOT
CONFIGURATION
L1P CACHE
DIRECT MAPPED
16K-BYTE TOTAL
PLL
(
x
1,
x
6,
x
12)
L2 CACHE MEMORY
256K-BYTE
POWER-DOWN
LOGIC
L1D CACHE
2-WAY SET-ASSOCIATIVE
16K-BYTE TOTAL
INSTRUCTION FETCH
C64
x
DSP CORE
.D1
.M1
.S1
.L1
.L2
.S2
.M2
.D2
INSTRUCTION DECODE
B REGISTER FILE
DATA PATH B
A REGISTER FILE
B31 - B16
A31 - A16
B15 - B0
A15 - A0
DATA PATH A
CONTROL
REGISTERS
CONTROL
LOGIC
INSTRUCTION DISPATCH
ADVANCED INSTRUCTION PACKET
TEST
ADVANCED
IN-CIRCUIT
EMULATION
INTERRUPT
CONTROL
VIDEO PORT 2
(VP2)
VIDEO PORT 0
(VP0)
8/10-BIT VP0
AND
McBSP0
OR
McASP0
CONTROL
VCXO
INTERPOLATED
CONTROL
PORT (VIC)
OR
VIDEO PORT 1
(VP1)
8/10-BIT VP1
AND
McBSP1
OR
McASP0
DATA
OR
HPI32
OR
HPI16
OR
AND
GP0
I2C0
IC
Summary of Contents for Ipels PCS-G50
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Page 191: ...PCS G50 G50P 8 7 8 7 CPU 382 B SIDE SUFFIX 12 13 A B C D 1 2 3 4 CPU 382 CPU 382 ...
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Page 200: ...Printed in Japan Sony Corporation 2005 6 22 2005 PCS G50 UC PCS G50P CE E 9 968 181 01 ...