— 53 —
IC510 MSM518126-50JSDR1
VSS
26
D08
25
D07
24
D06
23
D05
22
CAS
21
A4
14
A5
15
A6
16
A7
17
A8C
18
OE
19
VSS
1
D01
2
D02
3
D03
4
D04
5
WE
6
VCC
13
A3
12
A2
11
A1
10
A0
9
RAS
8
4
5
4
4
MEMORY
CELL
(1.048.576bit)
SENSE/
REFRESH AMP
INPUT/OUTPUT
CONTROL
ROW DECODER
COLUMN
DECODER
CLOCK
GENERATOR
OUTPUT
BUFFER
INPUT
BUFFER
ADDRESS BUFFER
9
8
8
52
51
F1
XVRST
50
XCS
49
SCK
48
SI
47
VSS
46
TDO
45
TCK
44
TMS
43
TDI
42
VDD
41
TRST
40
VSS
XTEST1
XTEST3
36
TD8
35
TD9
34
VDD
33
TD1O
53
VDD
54
XTEST4
55
XRST
56
SYSCLK
57
PDCLK
58
VSS
59
VSYNC
60
HSYNC
61
SO
62
FID
63
VDD
64
XIICEN
1/2
SYNC Gen.
and
Timing Controller
SIO and I
2
O-Bus
Controller
3
8
Sub Carrier
Gen.
Modulator
Dempx,
Level
Translator
and
Interpolator
4 : 2 : 2 to
4 : 4 : 4
Y, C/
Y, U, V
selector and
Interpolator
SYNC Slope
Gen.
Closed Caption Encoder
(for NTSC)
CSYNC
CHROMA
V
U
Y
BURST FLAG
37-39
-
TEST MODE
10
VDD
19
VSS
C7
C0
11-18
-
5
VSS
Y3
Y0
6-9
-
Y7
Y4
1-4
-
Delay
10bit
DAC
10bit
DAC
10bit
DAC
LPF
LPF
29 YO
28 AVSS2
27 AVDD2
26 VG
25 VB
24 COMPO
23 AVSS1
22 AVDD1
21 VREF
20 IREF
30 AVDD3
31 AVSS3
32 CO
4
4
8
IC511 CXD1913Q
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