DCM-M1
19
20
47
48
49
50
51
52
110
111
104
105
107
53
7
8
88
89
90
23
32
1
2
78
79
58
59
22
71
33
6
64
63
91
40
•
43
RXDO
•
RX_SYS
39
•
40
TXDO
•
TX_SYS
ADA_REST
TO AUDIO
(SEE PAGE 3-17)
AT_REST
AT_EXEC
AT_STRO
AT_INSL
AT_MUTE
AT_REC
AT_ATRAC2
AT_LEVEL3
SP_BEEP
HP_BEEP
SP_NMUTE
AMUTE
SP_VDD
PWR_DWN
MIC_ATT
XWIND
MIC_JACK_DET
HP_JACK_DET
W_JACK_DET
ADA_REST
MPEG2 RATE CONTRL
&
SYSTEM CONTROL
IC8501
AT_REST
AT_EXEC
AT_STRO
AT_INSL
AT_MUTE
AT_REC
AT_ATRAC2
AT_LEVEL3
4
80
1
87
98
94
95
97
MEC_RESET
CLK_OUT
XIMB
BS
XCS1
XRD
XWR
XCS2
5
12
9
MVP_RESEM
2D
11 X2CK
2Q
4JACK_DET
S_JACK_DET
C_OUT_OFF
S_OUT_OFF
4JACK_DET
S_JACK_DET
C_OUT_OFF
S_OUT_OFF
SP_BEEP
HP_BEEP
SP_NMUTE
AMUTE
SP_VDD
PWR_DWN
MIC_ATT
XWIND
MIC_JACK_DET
HP_JACK_DET
W_JACK_DET
ETHER_RESET
CN8007
(1/3)
CN4313
(2/3)
ETHER_RESET
DEV_RESET
RATE_RTS
RATE_TX
RATE_RX
RATE_CTS
XRESET
RATE_RTS
RATE_CTS
X1
X2
X8501
6.6MHz
9
TO SYSTEM CONTROL
(SEE PAGE 3-15)
12
TO MODE CONTROL
(SEE PAGE 3-24)
10
TO MD SERVO
(SEE PAGE 3-14)
11
G
V_REC_LED
V_REC_LED
A_REC_LED
A_REC_LED
RIGHT
RIGHT
TO LCD
(SEE PAGE 3-19)
TO ETHER
INTERFACE
(SEE PAGE 3-25)
H
DOWN
DRV_RESET
DRV_RESET
DOWN
173
59 58 57 84
17 18 19 68
62
170
164
168
166
167
XRST
A0 – A5
MB DATA
PROCESSOR
MOTION
ESTIMATION
ADAPTIVE PREFILTER
CHROMA POSTFILTER
DRAM INTERFACE
ENCODE SEQUENCE
CONTROL
HOST INTERFACE
VIDEO
INTERFACE
MB DATA
INTERFACE
D0-D15
XWE
CAS
RAS
SCLK
64M SDRAM
IC8602
MPEG2 ENCODER
IC8601
MPEG2 VIDEO PROCESSOR
IC8701
VE0 – VE7
VDD0 – VDD7
FSY
VDI0 – VDI7
ENDT0 – ENDT7
CLK
FSY_INT
MCLK_BUFF
WE
CAS
PAS
CLK
2
•
4
•
5
•
7
•
8
•
10
•
11
•
13
•
31
•
33
•
34
•
36
•
37
•
39
•
40
•
42
•
45
•
47
•
48
•
50
•
51
•
53
•
54
•
56
•
74
•
76
•
77
•
79
•
80
•
82
•
83
•
85
1
–
4
•
6
–
8
•
10
•
11
•
13
–
16
•
18
•
19
•
21
–
28
•
30
–
32
•
44
–
38
•
40
41
–
43
•
45
–
48
•
50
–
55
22
–
27
•
60
–
66
850D0 – 850D15
850D0 – 850D15
850A1 – 850A6
DRE0
–
DRE31
DR0
–
DR31
BA0, BA1,
ADE0
–
ADE9
BA0, BA1,
AD0
–
AD9
850A0 – 850A6
PLLI(FN)
XIMB
BS
XCS
XRD
XWR
106
103
101
102
127
l
134
•
136
l
143
137
•
138
•
140
–
143
•
145
–
148
•
150
–
153
•
155
•
156
157
•
158
•
160
l
163
119
l
125
D0
l
D15
A0
l
A6
HOST INTERFACE
MB DATA
INTERFACE
POSTFILTER
VIDEO
INTERFACE
DRAM INTERFACE
16M EDO DRAM
IC8702
16M EDO DRAM
IC8703
D-FF
IC8020(2/2)
VARIABLE LENGTH
CODING
ENCODER
BIT STREAM MANAGER
ENDT0 – ENDT7
FSY
CLK
SYS_BITI
05
SYS_BITO
HANDO
HANDI
VOUT0 – VOUT7
LOCAL
DECODER
VARIABLE LENGTH
DECODING
DQ0
l
DQ31
A0
l
A12
103
•
104
•
106
l
111
94
l
99
•
101
l
102
113
l
120
128
l
135
122
175
MEC0 – MEC7
SYS_MVP0 – SYS_MVP7
TO A/V DATA CONTROL,
VIDEO OUT
(SEE PAGE 3-8)
7
92
63 61 62
106
112
107
108
1
110
17 18
91
90
111
•
118
84
l
89
75
l
82
RST
TRST
XWR
XRD
XCS
A0 – A5
D0 – D7
12
–
14
•
16
–
19
•
21
–
24
•
26
–
36
•
38
–
43
•
45
–
48
2
–
5
•
7
–
10
•
41
–
44
•
46
–
49
21
–
24
•
27
–
32
49
•
50
•
52
–
57
•
59
•
60
RD0
–
RD31
RA0
–
RA9
XWE
BITO
BITI
HANDO
HANDI
RAS
CAS
VD0
–
VD31
MVP0
–
MVP7
ENDT0
–
ENDT7
VA0
–
VA9
VD0
–
VD15
VA0
–
VA9
VD16
–
VD31
VA0
–
VA9
WRITE
RAS
34
•
35
I/O1
l
I/O16
A0
l
A9
UCAS
•
LCAS
17 18
WRITE
RAS
34
•
35
UCAS
•
LCAS
850D0 – 850D7
850A0 – 850A5
DATA BUS
ADDRESS BUS
2
l
9
•
11
65
l
68
•
70
l
73
MAIN BOARD (2/7)
(SEE PAGE 4-33, 59)
2
–
5
•
7
–
10
•
41
–
44
•
46
–
49
21
–
24
•
27
–
32
I/O1
l
I/O16
A0
l
A9
6.6 MHz
REC/PB
1.12 Vp-p
27 MHz
REC/PB
3.52 Vp-p
3-9
3-10
3-5. MPEG ENCODE BLOCK DIAGRAM
Summary of Contents for MDDISCAM DCM-M1
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Page 69: ...DCM M1 4 5 4 6 4 7 4 8 4 1 FRAME SCHEMATIC DIAGRAM FRAME ...
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