DCM-M1
3
1
13
14
7
8
9
6
5
4
71
72
77
78
79
80
61
62
7
8
9
10
TPIP
PULSE TRANSFORMER
IC8807
CN8802
(2/2)
ETHER INTERFACE
IC8806
SRAM
IC8808
RD+
10BASE-T
ETHER ADAPTER
(2/2)
TPIN
TPOPA
IO BASE-T TRANSCEIVER
ENCODER/DECODER
DETA LINK CONTROLLER
BUFFER MANAGER
SYSTEM INTERFACE
TPOPB
TPONA
TPONB
CLKO
CLKI
CE
OE
WE
BCS
BOE
BWE
34
l
41
42
l
45
•
47
l
50
•
53
56
•
58
l
60
2
l
5
•
8
l
17
•
28
18
l
20
•
22
l
26
I/O1
l
I/O8
A0
l
A14
X8801
20MHZ
BD0 – BD7
BD0 – BD7
DATA BUS
BA0 – BA14
ADDRESS BUS
BD0 – BA14
30
32
33
27
6
1
RD–
TD+
TD–
DATA BUS
ADDRESS BUS
18
I
23
•
25
•
27
I
29
•
85
•
87
I
91
SD0 – SD15
SD8 – SD15
SA0 – SA3
BHE
SA0 – SA3
4
I
7
3
I
10
14
I
21
B0
I
B7
A0
I
A7
11
17
15
82
5
4
3
6
A2
A1
A0
A3
B2
B1
B0
B3
19
20
21
18
92
3
64
2
22
LEVEL SHIFT
IC8801
T/R
OE
3
I
10
14
I
21
B0
I
B7
A0
I
A7
2
22
LEVEL SHIFT
IC8802
T/R
OE
7
I
10
B4
I
B7
A4
I
A7
22
LEVEL SHIFT
IC8803
LEVEL SHIFT
IC8805
CN8801 (2/2)
TO SYSTEM CONTROL
(SEE PAGE 3-16)
DO – D15
RD&WT
A0 – A3
SBHE_CE2B
CS6_ETHER
ETHER_INT
ETHER_WAIT
ETHER_PWR
ETHER_RESET
DQMUL_ICIORD
DQMUU_ICIOWR
OE
10
9
A7
A6
B7
B6
14
LEVEL SHIFT
IC8804
10
A7
B7
22
OE
D8 – D15
D0 – D7
SD0 – SD7
A0 – A3
14
I
17
27
28
29
26
21
I
24
15
33
34
36
14
32
31
1
I
4
•
6
I
9
•
11
I
13
•
15
I
19
ECS
IOR
READY
HWRST
INT
IOW
K
ETHER BOARD (2/2)
(SEE PAGE 4-109)
TO MPEG ENCODE
(SEE PAGE 3-10)
G
05
20 MHz
REC/PB
1.28 Vp-p
3-25
3-26
3-13. ETHER INTERFACE BLOCK DIAGRAM
Summary of Contents for MDDISCAM DCM-M1
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