— 81 —
WFCK
GTOP
GFS
XPLCK
EFMO
RAOF
MVCI
TEST2
DIPD
DVSS
DICV
DIFI
DIFO
AVDD
ASYO
ASYI
BIAS
RFI
AVSS
CLTV
PCO
FILI
FILO
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
TEST3
AVDD
ADRT
ADRB
AVSS
SE
TE
AUX2
DCHG
APC
O
O
O
O
O
O
I
I
O(3)
–
I(A)
I(A)
O(A)
–
O
I(A)
I(A)
I(A)
–
I(A)
O(3)
I(A)
O(3)
I(A)
I(A)
I(A)
I(A)
I(A)
I(A)
O(A)
I(A)
–
I(A)
I(A)
–
I(A)
I(A)
I(A)
I(A)
I(A)
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
WFCK clock (7.35 kHz) signal output
(Playback: EFM decoder PLL
Recording: EFM encoder PLL) (Not used)
“H”: Opens playback EFM frame sync protection window (Not used)
“H”: Playback EFM sync and interpolation protection timing match (Not used)
EFM decoder PLL clock output (98 fs=4.3218 MHz)
Falling edge and EFM signal edge match (Not used)
EFM signal output (Recording) (Not used)
Internal RAM overflow detection signal output (decoder monitor output)
Outputs “H” when the disc rotation exceeds ±4F jitter margin during playback (Not used)
Digital-in PLL oscillation input (Fixed at “L”)
Test pin (Fixed at “L”)
Digital-in PLL phase comparison output
Internal VCO: (Frequency: Lown“H”)
External VCO: (Frequency: Lown“L”) (Not used)
Ground (Digital)
Digital-in PLL internal VCO control voltage input
Filter input when digital-in PLL internal VCO is used
Filter output when digital-in PLL internal VCO is used (Not used)
Power supply (+5V) (Analog)
Playback EFM full-swing output (L=VSS, H=VDD)
Playback EFM asymmetry comparate voltage input
Playback EFM asymmetry circuit constant current input
Inputs playback EFM RF signal from CXA1981AR (IC101)
Ground (Analog)
Decoder PLL master clock PLL VCO control voltage input
Decoder PLL master clock PLL phase comparison output
Decoder PLL master clock PLL filter input
Decoder PLL master clock PLL filter output
Inputs peak hold signal for light amount signal from CXA1981AR (IC101)
Inputs bottom hold signal for light amount signal from CXA1981AR (IC101)
Light amount signal from CXA1981AR (IC101)
Input of focus error signal from CXA1981AR (IC101)
Input of auxiliary signal from CXA1981AR (IC101)
Input of middle point voltage (+2.5V) from CXA1981AR (IC101)
A/D converter input signal monitor output (Not used)
Test input (Fixed at “L”)
Power supply (+5V) (Analog)
A/D converter operation range upper limit voltage input (Fixed at “H”)
A/D converter operation range lower limit voltage input (Fixed at “L”)
Ground (Analog)
Input of sled error signal from CXA1981AR (IC101)
Input of tracking error signal from CXD1981AR (IC101)
Auxiliary input 2 (Fixed at “L”)
Connected to ground
Laser APC input (Fixed at “L”)
Pin No.
Pin Name
I/O
Function
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