1-40
MVS-8000X/7000X
D301, D302 (D-1) :
+
1.0 V-1, -2
+
1.0 V power supply status indication.
Lights when the
+
1.0 V power is supplied.
D804 (K-1) : PLL UNLOCK
Indicates lock/unlock of the PLL (Phase Locked Loop) in
the FPGA.
If this LED lit, the PLL can possibly be unlocked.
D1301 (K-1) : CONF ERR
Indicates the con
fi
guration error of the FPGA.
If this LED lit, the FPGA can possibly be working incor-
rectly.
D501 (E-1) : CC1_UNLOCK
Indicates lock/unlock of the clock conditioner 1.
If this LED lit, the clock conditioner 1 can possibly be
unlocked.
D502 (E-1) : CC2_UNLOCK
Indicates lock/unlock of the clock conditioner 2.
If this LED lit, the clock conditioner 2 can possibly be
unlocked.
D1307 (E-1) : SDI1
Indicates the con
fi
guration error of the FPGA.
If this LED lit, the FPGA (IC2) can possibly be working
incorrectly.
D1304 (E-1) : SDI2
Indicates the con
fi
guration error of the FPGA.
If this LED lit, the FPGA (IC3) can possibly be working
incorrectly.
D1306 (E-1) : FC1/2
Indicates the con
fi
guration error of the FPGA.
If this LED lit, the FPGA (IC4) can possibly be working
incorrectly.
D1305 (E-1) : FC3/4
Indicates the con
fi
guration error of the FPGA.
If this LED lit, the FPGA (IC5) can possibly be working
incorrectly.
D1303 (F-1) : FC5/6
Indicates the con
fi
guration error of the FPGA.
If this LED lit, the FPGA (IC6) can possibly be working
incorrectly.
D1302 (F-1) : FC7/8
Indicates the con
fi
guration error of the FPGA.
If this LED lit, the FPGA (IC7) can possibly be working
incorrectly.
< Switch >
S601 (K-1) : RST
for design.
Summary of Contents for MVS-8000X System
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Page 58: ...Sony Corporation MVS 7000X SY MVS 8000X SY E 4 189 509 03 Printed in Japan 2011 5 08 2010 ...
