78
RCD-W10
Pin No.
1
2 to 6
7
8
9
10 to 15
16
17
18 to 21
22
23
24 to 29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59 to 66
67
68
69
70 to 77
78
79
80
81
I/O
—
O
O
—
—
I/O
—
—
I/O
—
—
I/O
O
O
O
O
—
—
I/O
I/O
I/O
I
O
O
O
O
O
O
O
O
O
O
—
—
—
—
I
I
I
O
O
I/O
I
—
—
I
I
I
I
I
Pin Name
DVSS
RA4 to RA8
RA9
DVDD
DVSS
IO0 to IO5
DVDD
DVSS
IO6 to IO9
DVDD
DVSS
IO10 to IO15
MON1
MON2
MON3
MON4
DVDD
DVSS
TEST0
TEST1
TEST2
WRITE
SSP2
SSP1
RAPC/C2F
WAPC
H11TO/FSQ
LDH/WRQ
ATEST3
ATEST1
WDAT
NWDAT
DVDD
DVSS
AVDD
AVSS
R1
VCNT1
DCNT1
PD1
ZINT
D0 to D7
SRSTNBY
AVDD
AVSS
SUA0 to SUA7
ZRD
ZCS
ZWR
ZRESET
Description
Ground terminal (digital)
Address signal output to the buffer RAM for audio data delay
Address signal output to the buffer RAM for audio data delay Not used (open)
Power 3.3V (DRAM I/F)
Ground terminal (digital)
Data input/output to the buffer RAM for audio data delay
Power 3.3V (digital)
Ground terminal (digital)
Data input/outputto the buffer RAM for audio data delay
Power 3.3V (DRAM I/F)
Ground terminal (digital)
Data input/output to the buffer RAM for audio data delay
Monitor output EFMG signal
Monitor output ATIPCRC/PCK/DATA signal (open)
Monitor output CDETR/CK2 signal
Monitor output EMP/LRCK signal (open)
Power 5V (digital)
Ground terminal (digital)
ENCERR signal output (pull-up)
TESTOUT signal output (pull-up)
TESTIN signal input (ground)
Write strategy signal control terminal
Servo sampling pulse output
Servo sampling pulse output
Laser sampling pulse output
Laser sampling pulse output
Running OPC sampling pulse output
LD control signal output for recording Not used (open)
Analog block test signal output (WE2)
Analog block test signal output Not used (open)
LD control signal output for recording
LD control signal output for recording
Power 5V (digital)
Ground terminal (digital)
Power supply 3.3V (analog) for the write strategy
Ground terminal (analog)
Analog terminal for the write strategy (fixed at “H”)
Analog terminal for the write strategy
Analog terminal for the write strategy Not used (open)
Analog terminal for the write strategy
Interrupt request signal output to the
µ
com (IC501)
Data input/output with the
µ
com (IC501)
Back up control terminal for CD-TEXT SRAM
Power 3.3V (analog) for CD-TEXT SRAM
Ground terminal (analog)
Command register selection address signal input
Data read out signal input from the
µ
com (IC501)
Chip select signal input from the
µ
com (IC501)
Data write signal input from the
µ
com (IC501)
Reset signal input
• IC201
LC89587-UK1-E CD DEC/ENC (CDR Board)
Summary of Contents for RCD-W10 - Cd/cdr Recorder/player
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