47
SCD-C555ES
• MAIN BOARD IC801 CXD2752R (DSP DECODER)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
I/O
—
I
I
I
—
O
O
O
I
I
I
—
O
O
O
O
—
O
O
O
O
O
O
O
O
I
Ipu
—
O
Ipu
Ipu
I
I
I
—
O
O
O
O
O
O
—
O
O
—
O
Description
Ground terminal for core.
Latch input terminal for microcomputer serial communication. Latches address and data at falling this signal.
Shift clock input terminal for microcomputer serial communication. Reads and shifts serial input data at the
rise-up of the clock that is input into this terminal. When reading out, read data changes at falling of clock that
inputs into this terminal.
Data input terminal for microcomputer serial communication. Inputs data and address with serial from
microcomputer.
Power terminal for core. 2.5 V.
Date output terminal for microcomputer serial communication. Hi-Z excluding output.
Output ready flag for microcomputer serial communication. When completing, outputs “L”. Open drain.
Output enable terminal for microcomputer serial communication. When using tri-state buffer externally, activates
by this terminal. When outputs “MSDATO”, “L” is shown.
Reset terminal. Resets entire IC on “L”. Clock that is output from EXCK01, EXCK02 and LRCK of output
terminal, doesn’t stop in resetting.
Soft mute terminal. Soft-mutes audio output with “H” and releases it with “L”.
Master clock input terminal. Inputs clock with 768 Fs (33.8688 MHz).
Ground terminal for input and output.
External output clock terminal 1. Upon setting, outputs 768 Fs, 512 Fs, 256 Fs and 128Fs.
External output clock terminal 2. Upon setting, outputs 768 Fs, 512 Fs, 256 Fs and 128Fs.
1Fs(44.1kHz) clock output terminal.
Frame signal output terminal.
Power terminal for input and output. 3.3 V.
Monitor output terminal. Upon setting of microcomputer, outputs a part of internal operation.
Monitor output terminal. Upon setting of microcomputer, outputs a part of internal operation.
Monitor output terminal. Upon setting of microcomputer, outputs a part of internal operation.
Monitor output terminal. Upon setting of microcomputer, outputs a part of internal operation.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Clock input terminal for testing. Fix “L”.
Input terminal for testing (pull-up). Keep open.
Ground terminal for core.
Output terminal for testing. Keep open.
Input terminal for testing (pull-up). Keep open.
Reset terminal for testing (pull-up). Input “power-on” reset signal or fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Power terminal for core. 2.5 V.
Output terminal for testing. Keep open.
Monitor terminal for DST related. Nothing is connected. For details, refer to part 3 DST_X_Bit of SACD
format book.
Output terminal for supplementary data (LSB).
Output terminal for supplementary data.
Output terminal for supplementary data.
Output terminal for supplementary data.
Ground terminal for input and output.
Output terminal for supplementary data.
Output terminal for supplementary data.
Power terminal for input and output. 3.3 V.
Output terminal for supplementary data.
Pin Name
VSC
XMSLAT
MSCK
MSDATI
VDC
MSDATO
MSREADY
XMSDOE
XRST
SMUTE
MCKI
VSIO
EXCKO1
EXCKO2
LRCK
FRAME
VDIO
MNT0
MNT1
MNT2
MNT3
TESTO
TESTO
TESTO
TESTO
TCK
TDI
VSC
TDO
TMS
TRST
TEST1
TEST2
TEST3
VDC
TESTO
XBIT
SUPDT0
SUPDT1
SUPDT2
SUPDT3
VSIO
SUPDT4
SUPDT5
VDIO
SUPDT6
Summary of Contents for SCD-C555ES - Super Audio Cd
Page 18: ...18 18 SCD C555ES 4 2 SCHEMATIC DIAGRAM RF SECTION Refer to page 40 for Waveforms IC B D 390p ...
Page 28: ...28 28 SCD C555ES 4 12 SCHEMATIC DIAGRAM AUDIO SECTION 2 2 Page 31 Page 31 IC B D ...
Page 29: ...29 29 SCD C555ES 4 13 SCHEMATIC DIAGRAM D POWER SECTION ...
Page 34: ...34 34 SCD C555ES 4 19 SCHEMATIC DIAGRAM HP SECTION TO AUDIO BOARD 1 2 Page 27 ...
Page 38: ...38 38 SCD C555ES 4 23 SCHEMATIC DIAGRAM POWER SECTION 27 ...
