52
SCD-C555ES
Description
Input terminal for testing. Fix “L”.
Ground terminal
Power terminal. 3.3.V.
Output terminal for testing. Keep open.
Ground terminal
Output terminal for testing. Keep open.
Ground terminal
Channel L DSD data output terminal
Power terminal. 3.3.V.
Channel R DSD data output terminal
Ground terminal
Channel LS DSD data output terminal
Ground terminal
Channel RS DSD data output terminal
Power terminal. 3.3 V.
Channel C DSD data output terminal
Ground terminal
Channel SW DSD data output terminal
Ground terminal
Phase reference signal input terminal for DSD output phase modulation
Phase reference signal output terminal for DSD output phase modulation
Bit clock input/output selection terminal for DSD data output. “L” is input (slave) and “H” is output (Master).
Bit clock output terminal for DSD data output. When BCKASL is “H”, bit clock is output from this terminal.
Bit clock input terminal for DSD data output. When BCKASL is “L”, input bit clock into this terminal.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Power terminal. 3.3 V.
Ground terminal
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Ground terminal
Master clock input terminal. Inputs clock with 768 Fs (33.8688 MHz).
Power terminal. 3.3 V.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Output terminal for testing. Keep open.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing. Fix “L”.
Input terminal for testing (pull down). Keep open or fix “L”.
Soft mute terminal. Soft-mutes audio output with “”H” and releases it with “L”.
Reset terminal. Resets entire IC on “L”. Clock that is output from FS128 and FS64 of output terminal, doesn’t
stop in resetting.
Ground terminal
Pin No.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin Name
TESTI
GND
VDD
TESTO
GND
TESTO
GND
DSAL
VDD
DSAR
GND
DSALS
GND
DSARS
VDD
DSAC
GND
DSASW
GND
PHREFO
PHREFI
BCKASL
BCKAO
BCKAI
TESTO
TESTO
VDD
GND
TESTI
TESTI
TESTI
TESTI
TESTI
TESTI
TESTO
TESTO
TESTI
TESTI
GND
MCKI
VDD
TESTO
TESTO
TESTO
TESTI
TESTI
TESTI
TESTI
TESTI
SMUTE
XRST
GND
I/O
I
—
—
O
—
O
—
O
—
O
—
O
—
O
—
O
—
O
—
O
I
I
O
I
O
O
—
—
I
I
I
I
I
I
O
O
I
I
—
I
—
O
O
O
I
I
I
I
Ipd
I
I
—
Ipd : Pull douwn input
Summary of Contents for SCD-C555ES - Super Audio Cd
Page 18: ...18 18 SCD C555ES 4 2 SCHEMATIC DIAGRAM RF SECTION Refer to page 40 for Waveforms IC B D 390p ...
Page 28: ...28 28 SCD C555ES 4 12 SCHEMATIC DIAGRAM AUDIO SECTION 2 2 Page 31 Page 31 IC B D ...
Page 29: ...29 29 SCD C555ES 4 13 SCHEMATIC DIAGRAM D POWER SECTION ...
Page 34: ...34 34 SCD C555ES 4 19 SCHEMATIC DIAGRAM HP SECTION TO AUDIO BOARD 1 2 Page 27 ...
Page 38: ...38 38 SCD C555ES 4 23 SCHEMATIC DIAGRAM POWER SECTION 27 ...