STR-DA6400ES
176
D VIDEO BOARD IC3604 YGV629-VZ (OSD CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
PLLVDD
-
Power supply terminal (+3.3V)
2
FILTER
I
Filter connection terminal for internal PLL
3
PLLVSS
-
Ground terminal
4
NC
-
Not used
5 to 10
PLLCTL5 to PLLCTL0
I
PLL setting terminal
11
DTCKS_N
I
Clock signal input terminal Not used
12
DTCK_IN
I
Clock signal input terminal Not used
13
VSS
-
Ground terminal
14
VDD
-
Power supply terminal (+3.3V)
15 to 22
D0 to D7
I/O
Two-way data bus with the video system controller and S-RAM
23
WAIT_N
O
Wait signal output to the video system controller
24
READY_N
O
Ready signal output terminal Not used
25
INT_N
O
Interrupt signal output to the video system controller
26
VDD
-
Power supply terminal (+3.3V)
27
VSS
-
Ground terminal
28
CS_N
I
Chip enable signal input from the video system controller
29
WR_N
I
Write enable signal input from the video system controller
30
RD_N
I
Read enable signal input from the video system controller
31 to 33
PS2 to PS0
I
Address signal input from the video system controller
34
SDOUT
O
Serial data output terminal Not used
35
SDIN
I
Serial data input terminal Not used
36
SCS_N
I
Chip select signal input terminal Not used
37
SCLK
I
Serial data transfer clock signal input terminal Not used
38
SER_N
I
CPU interface selection setting terminal Fixed at "H" in this set
39
RESET_N
I
Reset signal input from the video system controller "L": reset
40
VSS
-
Ground terminal
41
VDD
-
Power supply terminal (+3.3V)
42
MA0
O
Address signal output terminal Not used
43 to 47
MA1 to MA5
O
Address signal output to the
fl
ash memory
48
VSS
-
Ground terminal
49 to 54
MA6 to MA11
O
Address signal output to the
fl
ash memory
55
VDD
-
Power supply terminal (+3.3V)
56
VSS
-
Ground terminal
57 to 62
MA12 to MA17
O
Address signal output to the
fl
ash memory
63
VSS
-
Ground terminal
Address signal output to the
fl
ash memory
Power supply terminal (+3.3V)
Ground terminal
Write enable signal output to the
fl
ash memory
Output enable signal output to the
fl
ash memory
Two-way data bus with the
fl
ash memory
Ground terminal
Power supply terminal (+3.3V)
MD9, MD1
Two-way data bus with the
fl
ash memory
91
VSS
-
Ground terminal
92
VDD
-
Power supply terminal (+3.3V)
93, 94
MD8, MD0
I/O
Two-way data bus with the
fl
ash memory
95
RAHZ_N
-
Not used
96 to 98
XTEST2 to XTEST0
-
Not used
99
VSIN_N
I
Vertical sync signal input terminal Not used
100
HSIN_N
I
Horizontal sync signal input terminal Not used
101
NC
-
Not used
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