41
STR-KS1100
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IC Pin Function Description
MAIN BOARD IC1501 CXD9862R (DIGITAL AUDIO SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
-
Ground terminal
2
XRST
I
System reset signal input from the system controller "L": reset
3
EXTIN
I
Master clock signal input terminal Not used
4
LRCKI3
I
L/R sampling clock signal input terminal Not used
5
VDDI
-
Power supply terminal (+1.8V)
6
BCKI3
I
Bit clock signal input terminal Not used
7
PLOCK
O
PLL lock signal output terminal Not used
8
VSS
-
Ground terminal
9
MCLK1
I
System clock input terminal (13.9 MHz)
10
VDDI
-
Power supply terminal (+1.8V)
11
VSS
-
Ground terminal
12
MCLK2
O
System clock output terminal (13.9 MHz)
13
MS
I
Master/slave selection signal input terminal "L": internal clock, "H": external clock
Fixed at "L" in this set
14
SCKOUT
O
Master clock signal output to the stream processor
15
LRCKI1
I
L/R sampling clock signal input from the digital audio interface receiver
16
VDDE
-
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal input from the digital audio interface receiver
18
SDI1
I
Audio serial data input from the A/D converter
19
LRCKO
O
L/R sampling clock signal output to the stream processor
20
BCKO
O
Bit clock signal output to the stream processor
21
VSS
-
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver
23 to 25
SDO1 to SDO3
O
Audio serial data output to the stream processor
26
SDO4
O
Audio serial data output terminal Not used
27
SPDIF
O
SPDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal input from the digital audio interface receiver
29
BCKI2
I
Bit clock signal input from the digital audio interface receiver
30
SDI2
I
Audio serial data input from the digital audio interface receiver
-
Ground terminal
Acknowledge signal output to the system controller
I
Serial data input from the system controller
I
Serial data transfer clock signal input from the system controller
Serial data output to the system controller
I
Chip select input from the system controller
I
Write enable signal input from the system controller
SD-RAM chip enable output terminal Not used
39
GP14
O
Row address strobe signal output terminal Not used
40
VDDI
-
Power supply terminal (+1.8V)
41
VSS
-
Ground terminal
42
GP15
O
Column address strobe signal output terminal Not used
43
OE0
O
Output enable signal output to the S-RAM
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
-
Power supply terminal (+3.3V)
47
WMD1
I
External memory wait mode setting terminal Fixed at "H" in this set
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9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
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9
4
2
9
8
0
5
1
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3
6
7
3
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