VPR-129 (1/2)
CNP1
SDI IN CH1-CH8
CNL1
SDI IN CH9-CH16
CNE1
SDI OUT CH17-CH20
IC1
CN0201
SO-DIMM(8GB)
CN0301
SO-DIMM(8GB)
CN0401
SO-DIMM(8GB)
CN0501
SO-DIMM(8GB)
FPGA
IC2003
CLOCK
BUFFER
IC2002
CLOCK
BUFFER
BUF
IC1801,1802,
IC1803,1804,1805
FPGA CONFIG
FLASH 512M
APL CONFIG
FLASH 512M
IC1902
IC1901
LOCAL_BUS
BUF
IC2101,IC2102
CNC1
CPU_CLOCK
SYS_RESET
CONFIG
CONF_DONE
PCIE
PCIE_REFCLK
125M_REFCLK
to CPU(IC3)
from IC3204
from IC3203
BUF
IC2501,IC2052
D2501-D2516
CADEC
IC2
DIR/OE
CNB1
IC2302
VD
IC2303
FD
RESET/SLOT No.
IC2004
CLOCK
CLEANER
IC2005
CLOCK
CLEANER
CC_CTRL
27M/74M
CC_CTRL
74M
IC2402
JTAG
D2201
D2204
D2202
D2203
EPR2
CN2401
BUF
BUF
BUF
STATUS
BECON
POWER
INIT_ERR
S2303
D2402
CONF_ERR
RESET GEN
S3301
RE_CONFIG
CNP1
CNL1
CNE1
SDI OUT CH1-CH8
SDI OUT CH9-CH16
SDI OUT CH17-CH20
CLK_25M
DC-DC_PG
CPU_LCLK
CPU_LAD
CPU_IRQ
CPU_INIT
CPU_RESET
PLL_CONT
CGEN_CONT
PHY_RESET
PLL_CONT
to CPU(IC3)
from
IC3202
from
D-DCON.BLOCK
to IC3207
to IC3204
to IC3601,3701
to IC3206
D2001
D2002
CC UNLOCK
CC UNLOCK
DIVIDER
IC2001
VCLK
XVS-8000-C/XVS-8000
8-14