37
ZS-D10
6-16.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC801
µ
PD789477GC-A31-8BT (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1, 2
NC
—
Not used
3 to 5
VLC2 to VLC0
—
Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
6 to 9
COM0 to COM3
O
Common drive signal output to the liquid crystal display
10 to 26
SEG0 to SEG16
O
Segment drive signal output to the liquid crystal display
27 to 33
NC
O
Not used
34
A-MUTE
O
Audio muting on/off control signal output terminal “H”: muting on
35
SCL
O
Serial data transfer clock signal output to the EEPROM
36
SDA
I/O
Two-way data bus with the EEPROM
37
INIT
O
Initial setting signal output terminal
38
AVDD
—
Power supply terminal (+3.3V) (for A/D converter)
39
DIGITAL OUT
I
Digital out is used/not used setting input terminal
“L”: digital out is used (fixed at “L” in this set)
40
CD-DOOR
I
CD lid open/close detect switch input terminal “L”: CD lid is closed, “H”: CD lid is opened
41
SIMUKE
I
Destination setting input terminal
42
NC
I
Not used
43, 44
KEY-1, KEY-2
I
Top panel key input terminal (A/D input)
45
KEY-3
I
Test mode setting input terminal
46
C-FSEQ
I
Synchronizing signal detection signal input from the digital signal processor
47
AVSS
—
Ground terminal (for A/D converter)
48
RMC
I
Remote control signal input terminal
49
REG CHK
I
Regulator check signal input of the AC input
50
WP
I
Wake up reading signal input terminal “H” active
51
NC
I
Not used
52
WRQ
I
Interruption detection signal input from the digital signal processor
53
C-DO
I
Serial data input from the digital signal processor
54
C-DI
O
Serial data output to the digital signal processor
55
C-CLK
O
Serial data transfer clock signal output to the digital signal processor
56
C-CE
O
Chip enable signal output to the digital signal processor
57
R-MUTE
O
Tuner muting on/off control signal output to the FM/AM PLL “L”: muting on
58
C-DRF
I
Focus on/off detection signal input from the digital signal processor
59
C-RES
O
System reset signal output to the digital signal processor “L”: reset
60
R-COUNT
I
PLL serial count data input from the FM/AM PLL
61
R-CLK
O
PLL serial data transfer clock signal output to the FM/AM PLL
62
R-DATA
O
PLL serial data output to the FM/AM PLL
63
R-CE
O
PLL chip enable signal output to the FM/AM PLL
64
V-CLOCK
O
Serial data transfer clock signal output to the electrical volume
65
V-DATA
O
Serial data output to the electrical volume
66
P-CON
O
Power on/off control signal output terminal “H”: power on
67
CD
O
Power on/off control signal output for the CD section “H”: power on
68
VL
O
Liquid crystal display drive bias control signal output terminal “L” active
69
NC
I
Not used
70
XT1
I
Sub system clock input terminal (32.768 kHz)
71
XT2
O
Sub system clock output terminal (32.768 kHz)
72
VDD
—
Power supply terminal (+3.3V)
Summary of Contents for ZS-D10 Marketing Specifications & Features
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