Introduction
SY-5EMM
19
Frequency Settings for Cyrix ™ Processors (Continued)
Processor
Frequency Setting
Ratio
Bus
Clock
AGP
Clock
PCI
Clock
Frequency
Setting: SW1
Cyrix M II - 350**
3.0 x
100MHz 66MHz 33MHz
** Set the proper CPU frequency according to the marking on the CPU.
Over specification is not guaranteed.
Step 5. Set JP8,JP9,JP10 for SDRAM frequency
JP8 is used to indicate the frequency of the CPU bus clock to the
ETEQ chipset.
JP9 and JP10 are used to determine that the SDRAM is running at
the frequency of the CPU bus clock or the AGP clock.
CPU BUS
Clock
AGP BUS
Clock
JP10
JP8
JP9
SDRAM Clock
66MHz
66MHz
1-2
2-3
2-3
66MHz
75MHz
75MHz
1-2
2-3
2-3
75MHz
2-3
1-2
1-2
55MHz
83MHz
55MHz
1-2
1-2
2-3
83MHz
2-3
1-2
1-2
63.4MHz
95MHz
63.4MHz
1-2
1-2
2-3
95MHz
2-3
1-2
1-2
66MHz
100MHz
66MHz
1-2
1-2
2-3
100MHz
2-3
1-2
1-2
75MHz
112MHz
75MHz
1-2
1-2
2-3
112MHz
2-3
1-2
1-2
82.6MHz
124MHz
82.6MHz
1-2
1-2
2-3
124MHz
Note: Use 8ns or faster SDRAM modules (PC100 compliant) when
SDRAM is set to run at the frequency of 95/100 MHz.
1 2 3 4 5 6
ON
