BIOS Setup Utility
SY-6IEB
47
CHIPSET FEATURES SETUP (Continued)
CHIPSET
FEATURES
Setting
Description
Note
Disabled
CPU-To-PCI IDE
Posting
Enabled
Use this default setting
Default
Disabled
Default
System BIOS
Cacheable
Enabled
The ROM area F0000H-
FFFFFH is cacheable.
Disabled
Default
Video BIOS
Cacheable
Enabled
The video BIOS C0000H-
C7FFFH is cacheable.
Disabled
Default
Video RAM
Cacheable
Enabled
The ROM area A0000-
BFFFF is cacheable.
8 BIT I/O
Recovery Time
1
NA,2-8
Use the default setting
Default
16 BIT I/O
Recovery Time
1
NA,2-4
Use the default setting
Default
Disabled
Default
Memory Hole At
15M-16M
Enabled
Some interface cards will
map their ROM address to
this area. If this occurs,
select [Enabled] in this field.
Passive Release
Enabled
Use the default setting
Default
Delayed
Transaction
Enabled
Use the default setting
Default
AGP Aperture
Size
64
4-256MB
AGP could use the DRAM
as its video RAM. Choose
the DRAM size that you
wish to allocate as video
RAM.
Default
Summary of Contents for SY-6IEB
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