Motherboard Description
SY-7VBA 133
11
Dual copies of MA signals for improved drive
Optional bank-by-bank ECC (single-bit error correction and multi-
bit error detection) or EC(error checking only) for DRAM integrity
Two-bank interleaving for 16Mbit SDRAM support
Two-bank and four bank interleaving for 64Mbit SDRAM support
Independent SDRAM control for each bank
Seamless DRAM command scheduling for maximum DRAM bus
utilization (e.g., precharge other banks while accessing the current
bank)
Four cache lines (16quadwords) of CPU to DRAM write buffers
Four cache lines of CPU to DRAM read prefetch buffers
Read around write capability for non-stalled CPU read
Speculative DRAM read before snoop result
Burst read and write operation
x-2-2-2-2-2-2-2 bank-to-back accesses for EDO DRAM from CPU
or from DRAM controller
x-1-1-1-1-1-1-1 back-to back accesses for SDRAM
BIOS shadow at 16KB increment
Decoupled and burst DRAM refresh with staggered RAS timing
CAS before RAS or self refresh
Summary of Contents for SY-7VBA 133
Page 99: ...95 ...
