BIOS Setup Utility
SY-7VDA
70
CPU & PCI Bus Control
Setting
Description
Note
Disabled
CPU to PCI
Write Buffer
Enabled
When this field is
Enabled,
writes
from the CPU to the PCI bus are
buffered, to compensate for the
speed differences between the CPU
and the PCI bus. When
Disabled
,
the writes are not buffered and the
CPU must wait until the write is
complete before starting another
write cycle.
Default
Disabled
PCI Master 0
WS Write
Enabled
When
Enabled,
writes to the PCI
bus are executed with zero wait
states.
Default
PCI Delay
Disabled
Default
Transaction
Enabled
The chipset has an embedded 32-bit
posted write buffer to support delay
transactions cycles. Select
Enabled
to support compliance with PCI
specification version 2.1.
Summary of Contents for SY-7VDA
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