Drivers installation
SY-K7VLM-B
60
After you have completed the changes, press [Esc] and follow the
instructions on your screen to save your settings or exit without saving.
The following table describes each field in the Advanced Chipset Features
Menu and how to configure each parameter.
3-3.1 CHIPSET FEATURES SETUP
CHIPSET
FEATURES
Setting
Description
Note
Enabled
Default
DRAM
Timing By
SPD
Disabled
If enable the DRAM will auto
detect the DRAM timing.
DRAM Clock
133M
default
100M
This item allows you to control the
DRAM speed.
SDRAM Cycle
Length
3
2
When synchronous DRAM is
installed, the number of clock
cycles of CAS latency depends on
the DRAM timing. Do not reset
this field from the default value
specified by the system designer.
Default
4 Bank
Default
Disabled
Bank
Interleave
2 Bank
Increase DRAM performance.
Disabled
Enabled
Default
PCI Master
Pipeline Req
Disabled/Enabled PCI Master
Pipeline Req.
Disabled
Default
Memory Hole
Enabled
Some interface cards will map
their ROM address to this area. If
this occurs, select [Enabled] in this
field.
Disabled
P2C/C2P
Concurrency
Enabled
This item allows you to
enable/disable the PCI to CPU,
CPU to PCI concurrency
Default
Summary of Contents for SY-K7VLM-B
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