Motherboard Description
SY-P4IS2
9
AGP/PCI using PCI semantics and from the Hub Interface to Dram
will be snooped on the system bus. Memory accesses whose
addresses lie within the AGP aperture are translated using the AGP
address translation table, regardless of the originating interface.
1-6.3 DRAM Interface
The Intel® 845 chipset memory controller directly supports one
channel of PC133 SDRAM memory. The Intel® 845 chipset
memory interface supports SDR SDRAM devices with densities of
64-Mb, 128-Mb, 256-Mb, and 512-Mb technoloty. The Intel® 845
chipset memory interface also supports variable page sized of 2KB,
4KB, 8KB, and 16KB. Page size is individually selected for every
row and a maximum of 8 pages per DIMM may be opened
simultaneously.
Technology
SDR (PC133) Maximum
64 Mb
384 MB
128 Mb
768 MB
256 Mb
1.5 GB
512 Mb
3 GB
The memory interface provides optional ECC error checking for
DRAM data integrity. During DRAM writes, ECC is generated on a
QWORD (64bit) basis. Because the Intel® 845 chipset MCH stores
only entire cache lines in its internal buffers, partial QWORD writes
initially cause a read of the underlying data, and their write-back
into memory is no different from that of a complete cache line.
During DRAM reads, and the read of the data that underlies partial
writes, the MCH supports detection of single-bit and multiple-bit
errors, and will correct single bit errors when correction is enabled.
1-6.4 AGP Interface
A single AGP component or connector (not both) is supported by the
Intel® 845 chipset MCH AGP interface. The AGP buffers operate
only
in 1.5V mode. They are not 3.3V safe.
The AGP interface supports 2x/4x AGP signaling and 2x/4x Fast
Summary of Contents for SY-P4IS2
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