Motherboard Description
SY-P4IS2
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Writes. AGP semantic cycles to DRAM are not snooped on the
system bus. PCI semantic cycles to DRAM are snooped on the
system bus. The MCH supports PIPE# or SBA[7:0] AGP address
mechanisms, but not both simultaneously. Either the PIPE# or the
SBA[7:0] mechanism must be selected during system initialization.
Both upstream and downstream addressing is limited to 32 bits for
AGP and AGP/PCI transactions. The MCH contains a 32 deep AGP
request queue. High priority accesses are supported. All accesses
from the AGP/PCI interface that fall with in the Graphics Aperture
address range pass through an address translation mechanism with
fully associative 20 entry TLB. Accesses between AGP and Hub
Interface are limited to memory writes originating from the Hub
Interface destined for AGP. The AGP interface is clocked from a
dedicated 66MHz clock (66 IN). The AGP-to-host/core interface is
asynchronous.
1-6.5 Hub Interface
The 8-bit Hub Interface connects the MCH to the Intel ICH2. All
communication between the MCH and the Intel ICH2 occurs over
the Hub Interface. The Hub Interface runs at 66 MHz/266 MB/s.
Aside from the obvious traffic types, the following communication
also occur over Hub Interface:
l
Interrupt related messages
l
Power management events as messages
l
SMI, SCI, and SERR error indication messages
It is assumed that the Hub Interface is always connected to an Intel
ICH2.
1-6.6 MCH Clocking
The MCH has the following clock input pins:
l
Differential BCLK for the host interface
l
66MHz clock input for the AGP and Hub Interface
Clock Synthesizer chip(s) are responsible for generating the system
Host clocks, AGP and Hub Interface clocks, and PCI clocks. The
Summary of Contents for SY-P4IS2
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