PulseBlasterDDS
Specifications
DDS Specifications
•
100 MHz reference clock oscillator (other frequencies available upon request)
•
0.047 Hz frequency resolution (32 bits)
•
16 loadable frequency registers for agile frequency modulation/switching/selection (32 bits
each)
•
Two sets of 16 loadable phase-offset registers for agile phase modulation/switching/selection
(12 bits each)
•
0.09
°
phase resolution (12 bits)
•
40 ns phase switching latency
•
40 ns frequency switching latency (phase continuous)
•
phase coherent switching
•
10 dBm RF output power
•
50 ohm output impedance
•
SMA connectors
•
30 MHz 3dB bandwidth
•
RF Output capable of outputting DC at programmed output level (using phase offset)
TTL Specifications
•
10 individually controlled digital output lines (TTL levels; one of the output lines has a dual use
and functions as a phase reset for the DDS generator)
•
variable pulses/delays for every TTL line
•
25 mA output current per TTL line
•
output lines can be combined to increase the max. output current
Common Parameters (DDS and TTL Specifications)
•
90 ns shortest pulse/interval per instruction
•
2 years longest pulse/interval per instruction
•
10 ns pulse/interval resolution
•
RF and TTL pulses are synchronized
•
32k max. memory space
•
external triggering and reset – TTL levels
Pulse Program Control Flow (Common)
•
loops, nested 8 levels deep
•
20 bit loop counters (max. 1,048,576 repetitions)
•
subroutines, nested 8 levels deep
•
wait for trigger - 80 ns latency, adjustable to 2 years in duration
•
Approximately 2 MHz max. re-triggering frequency (based on the latency of the WAIT opcode)
9/20/20058
www.spincore.com
