Hardware layout and configuration
UM1974
56/82
DocID028599 Rev 7
CN9
21
D68
I2C_B_SDA
PF0
I2C_2
-
23
GND
GND
-
ground
25
D67
CAN_RX
PD0
CAN_1
27
D66
CAN_TX
PD1
29
D65
I/O
PG0
I/O
2
D51
USART_B_SCLK
PD7
USART_2
4
D52
USART_B_RX
PD6
6
D53
USART_B_TX
PD5
8
D54
USART_B_RTS
PD4
10
D55
USART_B_CTS
PD3
12
GND
GND
-
ground
14
D56
SAI_A_MCLK
PE2
(3)
SAI_1_A
16
D57
SAI_A_FS
PE4
18
D58
SAI_A_SCK
PE5
20
D59
SAI_A_SD
PE6
22
D60
SAI_B_SD
PE3
SAI_1_B
24
D61
SAI_B_SCK
PF8
26
D62
SAI_B_MCLK
PF7
28
D63
SAI_B_FS
PF9
30
D64
I/O
PG1
I/O
Right Connectors
CN7
1
D16
I2S_A_MCK
PC6
I2S_2
-
3
D17
I2S_A_SD
PB15
5
D18
I2S_A_CK
PB13
(4)
7
D19
I2S_A_WS
PB12
9
D20
I2S_B_WS
PA15
I2S_3 / SPI3
11
D21
I2S_B_MCK
PC7
13
D22
I2S_B_SD/
SPI_B_MOSI
PB5
15
D23
I2S_B_CK/ SPI_B_SCK
PB3
17
D24
SPI_B_NSS
PA4
Table 17. NUCLEO-F429ZI and NUCLEO-F439ZI pin assignments (continued)
Connector Pin
Pin
name
Signal name
STM32
pin
Function
Remark
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