UM1065
Hardware layout and configuration
Doc ID 018640 Rev 4
2.16 Ethernet
The STM3221G-EVAL evaluation board enables 10/100M ethernet communication by a
PHY DP83848CVV (U5) and integrated RJ45 connector (CN7). Both MII and RMII interface
modes can be selected by setting jumpers JP5, JP6 and JP8 as listed below:
Note:
1
A test point (TP2) is available on the board for the PTP_PPS feature test.
2
The Ethernet PHY, U5, can be powered down by regulating PB14.
3
In RMII mode it is not possible to use MCO to output the 50 MHz clock to PHY due to the
PLL limitation explained in chapter 2.6.5 of STM32F20x & STM32F21x Errata sheet
(ES0005). In such a case it is possible to provide the 50 MHz clock by soldering a 50 MHz
oscillator (ref SM7745HEV-50.0M or equivalent) on the U3 footprint located under CN3 and
also removing jumper on JP5. This oscillator is not provided with the board.
Table 11.
Ethernet related jumpers and solder bridges
Jumper
Description
JP8
JP8 selects MII or RMII interface mode.
To enable MII, JP8 is not fitted.
To enable RMII interface mode, JP8 is fitted.
Default setting: Not fitted.
JP6
To enable MII interface mode, set JP6 as shown (Default setting):
To enable RMII interface mode, set JP6 as shown:
JP5
To provide 25 MHz clock for MII or 50 MHz clock for RMII by MCO at PA8, set
JP5 as shown (Default setting):
To provide 25 MHz clock by external crystal X1 (for MII interface mode only) set
JP5 as shown:
When clock is provided by external oscillator U3, JP5 must not be fitted (Default setting).
SB1
SB1 selects clock source only for RMII mode.
To connect the clock from MCO to RMII_REF_CLK, close SB1.
The resistor R212 has to be removed in this case.
Default setting: Open.
3
2
1
3
2
1
3
2
1
3
2
1
