S/AI
Hardware Reference
Page 12 of 52
3.3 Reset
S are equipped with circuitry for generating power-up reset from the supply voltage
VSUP, as well as brownout detection.
During power-up, reset is kept until the supply voltage VSUP has reached the minimal operating
voltage. VSUP risetime has to comply with Table 1 for power-up reset to function properly. A reset
is also generated when VSUP falls below the threshold of the brownout detector (1,6V .. 1,7V with
a hysteresis of about 30mV), and is released when VSUP rises above that threshold.
By holding pin B-1 (EXT-RES#)
at ≤ VSUP*0,3V for t
HOLDRESETNORMAL
≥ 0,2µs, an external reset (
pin
reset
) is generated. This pin has a fixed internal pull-up resistor (R
PU
= 11k
Ω ... 16kΩ). EXT-RES#
may be left open if not used.
Note:
The reset-functionality associated with pin EXT-RES# is shared with the serial wire debug
feature (refer to 3.12). Inside the S module, EXT-RES# is connected to SWDIO via a
150R resistor. During a debug session the external reset function is not available; asserting of
EXT-RES# to
any
level should be avoided.
S
E-6,F-6
VSUP
GND
+3V3
EXT-RES#
B-1
Reset-Switch is optional
Please Note: EXT-RES# of S has approx. 13k internal pullup.
1k
Reset signal is optional
Host MCU
GPIO
VDD
Figure 3: S Example Reset
