Chapter 3
Power-On Self-Test (POST)
3-7
IOMMU Base Address Reg Test
IOMMU TLB Flush Entry Test
IOMMU TLB Flush All Test
SBus Read Time-out Test
EBus Read Time-out Test
D-Cache RAM NTA Test
D-Cache TAG NTA Test
I-Cache RAM NTA Test
I-Cache TAG NTA Test
Memory Address Pattern Test
FPU Register File Test
FPU Misaligned Reg Pair Test
FPU Single-precision Tests
FPU Double-precision Tests
FPU SP Invalid CEXC Test
FPU SP Overflow CEXC Test
FPU SP Divide-by-0 CEXC Test
FPU SP Inexact CEXC Test
FPU SP Trap Priority > Test
FPU SP Trap Priority < Test
FPU DP Invalid CEXC Test
FPU DP Overflow CEXC Test
FPU DP Divide-by-0 CEXC Test
FPU DP Inexact CEXC Test
FPU DP Trap Priority > Test
FPU DP Trap Priority < Test
PROC0 Interrupt Regs Tests
Soft Interrupts OFF Test
Soft Interrupts ON Test
PROC0 User Timer Test
PROC0 Counter/Timer Test
DMA2 E_CSR Register Test
LANCE Address Port Tests
LANCE Data Port Tests
DMA2 D_CSR Register Test
DMA2 D_ADDR Register Test
DMA2 D_BCNT Register Test
DMA2 D_NADDR Register Test
ESP Registers Tests
DMA2 P_CSR Register Test
DMA2 P_ADDR Register Test
DMA2 P_BCNT Register Test
PPORT Registers Tests
NVRAM Access Test
TOD Registers Test
CODE EXAMPLE 3-1
Tests POST Runs
Summary of Contents for SPARCstation 4 110
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