Appendix C
Functional Description
C-3
C.1.1
UPA
The UPA is a cache-coherent processor-to-memory interconnect. A key advantage of
the UPA processor-to-memory interconnect is a scalable bandwidth through support
of multiple bussed interconnects for both data
and address. Other advantages include more bandwidth, high-performance graphics
support with two-cycle, single-word writes on the 64-bit UPA data bus, and
centralized coherence and memory controller functions. The UPA consists of the
following, as implemented on the system board:
■
Eighteen BMX ASICs
■
The BMX ASICs connect the 144-bit UPA processor data bus to a 288-bit
memory data bus and a 72-bit UPA data bus for graphics and I/O devices
■
The memory path is 64 bits
■
The processor shares a UPA address bus (UPA address bus 0) with the SYSIO
ASIC; a second address bus (UPA address bus 1) supports slave UPA connection
to the expansion slot for graphics capability
■
Low voltage transistor-transistor logic (TTL) voltage levels for signal input
■
Up to 100 MHz operation (10-nanosecond system cycle time). A
6-nanosecond UltraSPARC operation results in a 12-nanosecond UPA operation.
A 5-nanosecond UltraSPARC results in a 10-nanosecond UPA operation
C.1.2
SBus
The system unit or server uses the IEEE 1496 SBus specification. This includes:
■
16.6-MHz to 25-MHz operation. Default frequency is 25 MHz; independent of
processor and UPA operating frequencies
■
Extended transfer mode (64-bit data path)
■
Transfer sizes to 64 bytes (maximum)
■
Parity
■
Dedicated interrupts per SBus slot.
The system unit or server supports two SBus slots. The slots are configured in a
stacked configuration.
C.1.3
UltraSPARC Processor
The UltraSPARC processor is mounted on a module that is plugged into the system
board. The UltraSPARC processor has the following features:
■
SPARC V9 compatibility
Summary of Contents for Ultra 1 Series
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