Chapter 2: Installation
2-21
IP
MI C
ODE
M
AC C
ODE
DESIGNED IN USA
FAN3
A
C
LE1
JTP
M1
JCOM1
1
JB1
1
LEB2
JLAN1
JLAN2
MH1
JI2C2
1
JBR1
3
JP
ME2
1
JWD1
1
3
1
JP1
1
JP2
JI2C1
JB3
1
JB2
1
JIB1
1
JPB1
JPL1
JPG1
JVRM1
3
JPF2
1
3
JVRM2
1
JPF1
1
JIP
MB1
JSD1
JSD2
LEDPWR
LE8
LEDBMC
C
JUSBRJ45
+
+
JB
T1
BT1
J23
JF1
JPCIE1
SXB2
SXB1
SSA
TA0
SSA
TA1
SA
TA2
SA
TA1
JVGA
JSTBY1
JUIDB1
BIOS LICENSE
IB GUID
BAR C
ODE
1.01
RE
V:
X10DR
T-H
IP
MI_LAN
USB0/1(3.0)
JIB1:
1-2:ENABLE
2-3:DISABLE
CHASIS INTRUSION JL1:
JWD1:
2-3:NMI 1-2:RST
S-SA
TA1
:
I-SA
TA0
I-SA
TA1
:CPU2 SXB2 PCI-E 3.0 X8(INX4)
CPU1 SXB1 PCI-E 3.0 X8(INX4)
CPU1 SL
O
T1 PCI-E 3.0 X16
S-SA
TA0
JBR1:
JP
ME2:
1-2:NORM
AL
2-3:ME M
ANUF
ATURING MODE
1-2:NORM
AL
2-3:BIOS REC
OVER
Y
1-2:ENABLE
JI2C1/JI2C2:
I2C BUS FOR SL
O
T
2-3:DISABLE
UID
:
P1-DIMM
A1
P1-DIMMB1
VGA
P2-DIMMG1 P2-DIMMH1
CPU1
CPU2
COM1
LAN2
P2-DIMME1
P2-DIMMF1
P1-DIMMD1
LAN1
1-2:ENABLE
2-3:DISABLE
JPG1:VGA
P1-DIMMC1
TP
M/POR
T80
JPL1:LAN
JPB1:BMC
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE 1-2:ENABLE
SA
TA DOM PWR
JBT1:
CMOS
CLEAR
CLOSE 1st
OPEN 1st
CLOSE 1st
OPEN 1st
LEB1
QSFP
P2-DIMME1
P2-DIMMF1
P2-DIMMG1 P2-DIMMH1
P1-DIMM
A1
P1-DIMMB1
2-7 Connecting Cables
A. IPMB
A
IPMB I
2
C SMB
A System Management Bus header
for the IPMI slot is located at JIPMB1.
Connect an appropriate cable here to
use the IPMB I
2
C connection on your
system.
SMB Header
Pin Definitions
Pin# Definition
1
Data
2
Ground
3
Clock
4
No Connection