B-5
Appendix B: BIOS POST Checkpoint Codes
Checkpoint Code Description
4Ch
The memory below 1 MB has been cleared via a soft reset. Clearing the memory
above 1 MB next.
4Dh
The memory above 1 MB has been cleared via a soft reset. Saving the memory size
next. Going to checkpoint 52h next.
4Eh
The memory test started, but not as the result of a soft reset. Displaying the fi rst
64 KB memory size next.
4Fh
The memory size display has started. The display is updated during the memory
test. Performing the sequential and random memory test next.
50h
The memory below 1 MB has been tested and initialized. Adjusting the displayed
memory size for relocation and shadowing next.
51h
The memory size display was adjusted for relocation and shadowing.
52h
The memory above 1 MB has been tested and initialized. Saving the memory size
information next.
53h
The memory size information and the CPU registers are saved. Entering real mode
next.
54h
Shutdown was successful. The CPU is in real mode. Disabling the Gate A20 line,
parity, and the NMI next.
57h
The A20 address line, parity, and the NMI are disabled. Adjusting the memory size
depending on relocation and shadowing next.
58h
The memory size was adjusted for relocation and shadowing. Clearing the Hit
<DEL> message next.
59h
The Hit <DEL> message is cleared. The <WAIT...> message is displayed. Starting
the DMA and interrupt controller test next.
60h
The DMA page register test passed. Performing the DMA Controller 1 base register
test next.
62h
The DMA controller 1 base register test passed. Performing the DMA controller 2
base register test next.
65h
The DMA controller 2 base register test passed. Programming DMA controllers 1
and 2 next.
66h
Completed programming DMA controllers 1 and 2. Initializing the 8259 interrupt
controller next.
67h
Completed 8259 interrupt controller initialization.
7Fh
Extended NMI source enabling is in progress.
80h
The keyboard test has started. Clearing the output buffer and checking for stuck
keys. Issuing the keyboard reset command next.
81h
A keyboard reset error or stuck key was found. Issuing the keyboard controller
interface test command next.
82h
The keyboard controller interface test completed. Writing the command byte and
initializing the circular buffer next.
83h
The command byte was written and global data initialization has completed. Check-
ing for a locked key next.
84h
Locked key checking is over. Checking for a memory size mismatch with CMOS
RAM data next.
85h
The memory size check is done. Displaying a soft error and checking for a password
or bypassing WINBIOS Setup next.
Summary of Contents for AS2041M-32R Plus
Page 1: ...AS2041M 32R AS2041M T2R USER S MANUAL 1 0 SUPER ...
Page 5: ...v Preface Notes ...
Page 16: ...1 6 AS2041M 32R 2041M T2R User s Manual Notes ...
Page 25: ...Chapter 2 Server Installation 2 9 Figure 2 4 Accessing the Inside of the System ...
Page 30: ...3 4 AS2041M 32R 2041M T2R User s Manual Notes ...
Page 67: ...Chapter 6 Advanced Chassis Setup 6 5 Figure 6 3 Installing the Air Shroud ...
Page 73: ...Chapter 6 Advanced Chassis Setup 6 11 Figure 6 6 Removing Replacing the Power Supply ...
Page 74: ...6 12 AS2041M 32R 2041M T2R User s Manual Notes ...
Page 94: ...A 2 H8QM3 2 H8QMi 2 User s Manual Notes ...
Page 102: ...B 8 AS2041M 32R 2041M T2R User s Manual Notes ...
Page 106: ...C 4 AS2041M 32R 2041M T2R User s Manual Notes ...
