Chapter 1: Introduction
1-9
1-2 Chipset Overview
The 3210 chipset, designed for use with the Quad Core/Dual Core Intel Xeon
3000 Series/3200 Series Processor, is comprised of two primary components: the
Memory Controller Hub (MCH) and the I/O Controller Hub ICH9R. In addition, the
PXH-V chip is used for added functionality. The X7SBi provides the performance
and feature-set required for cost-effective, power-efficient UP system platforms.
Memory Controller Hub (MCH)
The function of the MCH is to manage the data flow between four interfaces: the
CPU interface, the DDR2 System Memory Interface, the PCI Express Interface
(*Note Below), and the Direct Media Interface (DMI).
The MCH is optimized for a Quad Core/Dual Core Xeon 3000 Series/3200 se-
ries processor in the LGA775 Land Grid Array Package with a FSB frequency
of 800/1066/1333 MHz. The 3210 MCH supports 36-bit host bus addressing, al-
lowing the CPU to access to the entire 64 GB of the host address space. It also
has a 12-deep In-Order Queue to support up to 12 outstanding pipelined address
request on the host bus. It supports one or two channels of DDR2 SDRAM. The
3210 platform uses the ninth generation I/O Controller Hub (ICH9R) to provide I/O
related functions.
The Ninth Generation I/O Controller Hub (ICH9R)
The I/O Controller ICH9R provides the data buffering and interface arbitration re-
quired for the system to operate efficiently. It also provides the bandwidth needed
for the system to maintain its peak performance. The Direct Media Interface (DMI)
provides the connection between the MCH and the ICH9R. The ICH9R supports
up to six PCI-Express x8 Lanes, six Serial ATA ports and twelve USB 2.0 ports.
In addition, the ICH9R offers the Intel Matrix Storage Technology which provides
various RAID options for data protection and rapid data access. It also supports the
next generation of client management through the use of PROActive technology in
conjunction with Intel's next generation Gigabit Ethernet controller.
Intel ICH9R System Features
The I/O Controller Hub provides the I/O subsystem with access to the rest of the
system. Functions and capabilities include:
Advanced Power Management
•
SMBus 2.0 (I
•
2
C)
SST/PECI Fan Speed Control
•
SPI Flash
•
Low Pin Count (LPC) Interface
•
Note:
The Intel 3210 chipset does not support add-in graphics cards in the PCI-E
interface provided by the Memory Controller Hub (MCH).
Summary of Contents for Supero X7SBi
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