Tandy 1000 SL Technical Reference Manual Download

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Summary of Contents for 1000 SL

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Page 2: ...vices Power Supplies Keyboards D i s k Drives The Software section contains t h e following A Quick Reference l i s t of software i n t e r r u p t s for a l l device I O and system s t a t u s servic...

Page 3: ...ets 1 of 7 thru 7 of 7 C8000308 Rev B Sheet 1 of 1 Foldout PCB art Insert after the Main Logic Board schematics Silkscreen 1700378 Rev B Layer 1 Component Side Layer 2 GND Plane Layer 3 5V Plane Layer...

Page 4: ...on Schematic Fujitsu Custom IC Pin Signals Function Sheet 3 of 3 Foldout TEAC schematic pages Insert after the Section 3 Maintenance portion of the Disk Drive section PCBA Front Opt N Total Diagram PC...

Page 5: ...fresh Control 9 BIOS ROM Control 10 Reset Circuit 10 Wait State and Ready Logic 10 NMI Logic 12 8087 Control Logic 12 CPU Address Buffers 12 Data Buffers and Conversion Logic 12 1 0 Decode 13 Floppy D...

Page 6: ...Introduct ion...

Page 7: ...chrome and t h e color RGB monitor S i n c e t h e s e u n i t s are modular you can p l a c e them on t o p of t h e main u n i t or a t any c o n v e n i e n t l o c a t i o n The Tandy 1000 SL come...

Page 8: ...l e r 101 key Enhanced keyboard Custom p a r a l l e l p r i n t e r p o r t S e r i a l p o r t RS 232 C Audio i n t e r f a c e c i r c u i t t h a t s u p p o r t s i n t e r n a l 8 OHM s p e a k...

Page 9: ...Assembly Disassembly...

Page 10: ...l a Remove the top cover b Unplug all cables from the disk drive c Remove the 3 screws attaching the drive to the drive mounting tower d Slide the drive forward out of the drive mounting tower 3 Power...

Page 11: ...i s t o t h e rear and down t o clear t h e 3 hooks i n t h e bottom o f t h e c h a s s i s e Remove s p r i n g c l i p f r o m volume c o n t r o l knob post f Remove t h e 11 screws h o l d i n g...

Page 12: ...S AC HARNESS AC I N T L CAPACITOR 1000 P F D 400V TORROID CORE F A I R R I T E NUT KEPS 6 32 FAN 80MM 12 VDC SCREW lo T A P I T THREAD ENDPLATE POWER SUPPLY SCREW 6 32 X 5 16 C H A S S I S REAR D I S...

Page 13: ...W BUTTON RESET FRONT BUTTON RESET REAR SPRING RESET BUTTON CORD POWER 18 3 60 C LABEL SERIAL CSA NAMEPLATE LABEL SERIAL INT L LABEL SERVICE ADVISEMENT 6 LANG LABEL CAUTION 6 LANG LABEL EARTH GROUND IN...

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Page 16: ...nd disk drive by a series of cables The power supply is a 67W switching regulator type designed to provide adequate power capacity for a fully configured system that has all the option slots in use Th...

Page 17: ...c t i o n E1 E2 S e l e c t video I n t e r r u p t o n IRQ5 E2 E3 N o r m a l Video I n t e r r u p t Sound Input Output S a t e l l i t e Board Jumper F u n c t i o n El E2 E2 E3 S e l e c t Direct...

Page 18: ...Hz Clock is routed into the custom IC 879024 which generates the output signal CPUCLK The Clock Switch circuitry required to toggle the 8086 Microprocessor between 8 MHz and 4 MHz mode as well as the...

Page 19: ...a r t a memory c y c l e is d e t e r m i n e d i n t e r n a l t o t h e 8079024 custom IC The f o l l o w i n g t a b l e i n d i c a t e s t h e d e c o d i n g o f t h e CPU s t a t u s s i g n a...

Page 20: ...l System Option Memory Memory 0 0 0 1 0 1 2 1 0 3 1 1 256K 512K 512K 640K 384K 64OK 640K 768K Note T o t a l s y s t e m memory i n c l u d e s 128K of v i d e o memory Memory Option 0 is t h e power...

Page 21: ...t The reset output signals RSTIN is active low and generated when a power up condition is detected or when the reset button on the front of the computer is pressed The RSTIN signal is supplied to the...

Page 22: ...36 MHz 24 MHz Programmable W a i t S t a t e C o n t r o l Another method is c o n t r o l l e d by t h e d e v i c e b e i n g accessed u s i n g t h e IOCHRDY s i g n a l i n p u t t o t h e 8079024...

Page 23: ...8079024 custom IC provides the buffering of the address lines to the system AO Al9 are buffered and latched for the expansion bus slots and 1 0 peripherals ALE is used to latch AO A11 internal to the...

Page 24: ...cessary to interface the serial bit stream to or from the FDD to parallel bus of the system implement the commands necessary to operate the FDD of the the maintain information about the status of the...

Page 25: ...d data signals from the serial bit stream of the Floppy Disk Drive The FDC Support IC supports only MFM or Double density mode Disk Drive Interface All FDC outputs to the FDD are driven by high curren...

Page 26: ...dress inputs to the dynamic RAMS This MUX switches between video 6845 address and CPU address as well as between row and column address Also the video interface chip provides the RAM timing signals an...

Page 27: ...software timing functions Counter 1 is used for refresh function timing Counter 2 is connected to the sound circuit and its output can be read at port Hex 0062 Bit 5 Joystick Interface The joystick i...

Page 28: ...t s i g n a l is mixed w i t h t h e sound g e n e r a t o r s i g n a l and s u p p l i e d t o t h e a u d i o o u t p u t p i n The o u t p u t o f t h e 76496 e n a b l e s P o r t 61 B i t 4 whi...

Page 29: ...5 internal to the 8079024 custom IC acts as the bus master and along with the associated logic generates all bus control signals and address and data signals The DMA transfers continue for the number...

Page 30: ...abilities provide loopback functions of transmit receive and input output signals The 8079021 custom IC serial port is programmed by selecting the 1 0 address 3F8 3FE hex and writing data out to the p...

Page 31: ...al Name NMI IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IODl IODO IOCHRDY HLDA A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 I O I I O I O I O I O I O I O I O I O I 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 32: ...ith HLDA BUSALE is active high HLDA All HLDA is an Address Enable signal used to remove the CPU and other devices from the bus to allow DMA transfers to take place During HLDA active the DMA controlle...

Page 33: ...the data from the appropriate data bus ADO AD15 for 16 bit memory IODO IOD7 for 8 bit memory This line can be driven by the CPU Control IC or by the DMA controller through the CPU Control IC MEMW is a...

Page 34: ...m Video RAM A0000 BFFFF 128K Video RAM COOOO DFFFF 128K Expansion Memory EOOOO FFFFF 128K BIOS ROM Allocated Function System Memory System Memory and Video Display Memory or System Memory Reserved f o...

Page 35: ...2FF 0370 0377 0378 037F 03DO 03DF 03FO 03F7 03F8 0 3FF F u n c t i o n DMA F u n c t i o n I n t e r r u p t C o n t r o l l e r Timer PIO F u n c t i o n DMA Page R e g i s t e r NMI Mask R e g i s t...

Page 36: ...r e n t Word Count I n t e r n a l Flip FlOp 0 Read WO w7 I n t e r n a l F l i p F l o p 1 Read W8 Wl5 0002 DMA C o n t r o l l e r IOW 0 Channel 1 Base and C u r r e n t Address I n t e r n a l F l...

Page 37: ...el 2 C u r r e n t Word Count I n t e r n a l F l i p F l o p 0 Read W O W 7 I n t e r n a l F l i p F l o p 1 Read W8 Wl5 DMA C o n t r o l l e r IOW 0 c h a n n e l 3 Base and C u r r e n t Address...

Page 38: ...g X If B i t 0 1 4 0 Fixed P r i o r i t y 1 R o t a t i n g P r i o r i t y 5 0 L a t e W r i t e S e l e c t i o n 1 Extended W r i t e S e l e c t i o n X If B i t 3 1 6 O DREQ Sense A c t i v e Hi...

Page 39: ...B i t 1 Set Request B i t B i t s 3 7 DonI t C a r e IOR 0 Illegal OOOA D M A C o n t r o l l e r IOW 0 W r i t e S i n g l e Mask R e g i s t e r B i t D e s c r i p t i o n B i t s 0 1 B i t 1 B i...

Page 40: ...s f e r To Memory f 1 0 Read T r a n s f e r To Memory 1 1 I l l e g a l X I f B i t s 6 a n d 7 1 1 t B i t 4 0 1 A u t o i n i t i a l i z a t i o n Enable A u t o i n i t i a l i z a t i o n D i s...

Page 41: ...B i t D e s c r i p t i o n 0 0 C l e a r Channel 0 Mask B i t E n a b l e 1 0 C l e a r Channel 1 Mask B i t E n a b l e 2 0 C l e a r Channel 2 Mask B i t E n a b l e 3 0 C l e a r Channel 3 Mask B...

Page 42: ...Word 2 Bit 3 0 BitO 2 Determine The Interrupt Level Acted On When the SL Bit Is Active InterruptLevel 0 1 2 3 4 5 6 7 Bit 0 LO 0 1 0 1 0 1 0 1 Bit 1 Ll 0 0 1 1 0 0 1 1 Bit 2 2 0 0 0 0 1 1 1 1 Bits 5 7...

Page 43: ...o l l Command B i t s 5 6 B i t 5 B i t 6 S p e c i a l Mask Mode 0 0 N o Action 0 1 No Action 1 0 Reset S p e c i a l Mask 1 1 S e t S p e c i a l Mask B i t 7 0 0021 8259A I n t e r r u p t C o n t...

Page 44: ...1 5 0 6 1 7 Bits 3 7 0 Not Used Initialization Control Word 4 Bit 0 Type Of Processor 0 MCS 80 85 Mode 1 8086 8088 80286 Mode Bit 1 Type of End of Interrupt 0 Normal EO1 1 Auto EO1 Bits 2 3 Buffering...

Page 45: ...v i c e must g e n e r a t e a l o w t o high edge and t h e n remain a t a logic high l e v e l u n t i l s e r v i c e is acknowledged F a i l u r e t o do so r e s u l t s i n a Default S e r v i c...

Page 46: ...ode 1 X 1 0 Mode 2 X 1 1 Mode 3 1 0 0 Mode 4 1 0 1 Mode 5 0043 0047 8254 2 Timer B i t s 4 5 Read Load B i t 5 B i t 4 0 0 Counter L a t c h i n g O p e r a t i o n 0 1 Read Load LSB Only 1 0 Read Loa...

Page 47: ...a r d B i t 3 K e y b o a r d B i t 4 K e y b o a r d B i t 5 K e y b o a r d B i t 6 K e y b o a r d B i t 7 MSB 0061 P o r t B R e a d or W r i t e B i t D e s c r i p t i o n 0 1 8 2 5 3 G a t e 2...

Page 48: ...64 Reserved 0065 P l a n a r C o n t r o l R e g i s t e r B i t D e s c r i p t i o n 0 Hard Disk P o r t S e l e c t 1 P a r a l l e l P o r t S e l e c t 2 Video P o r t S e l e c t 3 Floppy Disk P...

Page 49: ...r e s s A 1 9 DMA C h a n n e l 0 1 Page R e g i s t e r Write O n l y A d d r e s s D e s c r i p t i o n B i t 0 A d d r e s s A 1 6 B i t 1 A d d r e s s 1 7 B i t 2 A d d r e s s A 1 8 B i t 3 A d...

Page 50: ...F3 A 1 F7 F3 A 1 F7 F3 A 1 FB A 1 F8 F4 A2 F8 F4 A2 F8 F4 A2 NFO A2 F9 F5 A3 F9 F5 A3 F9 F5 A3 NFI A3 Update Tone Frequency 1 A d d i t i o n a l Frequency Data Update Tone A t t e n u a t i o n 1 Up...

Page 51: ...n t e r r u p t Allowed DMA I n t e r r u p t Enable DMA EOP I n t e r r u p t D i s a b l e d DMA EOP I n t e r r u p t Enabled Sound D i v i d e r Sync Enable S y n c h r o n i z a t i o n D i s a b...

Page 52: ...i t 5 R e s e r v e d B i t s 6 7 Waveshape Select B i t 7 B i t 6 Waveshape Selected 0 0 Pulse 0 1 R a m p 1 0 T r i a n g l e 1 1 R e s e r v e d 0OC5 0OC6 R ead D i r e c t R e a d of DAC w h e n...

Page 53: ...cal P o s i t i o n 2 L X H o r i z o n t a l P o s i t i o n 3 L Y Vertical P o s i t i o n 4 R B u t t o n 1 L o g i c 0 B u t t o n P r e s s e d 5 R B u t t o n 2 Logic 0 B u t t o n P r e s s e d...

Page 54: ...i t 3 4 B i t 4 5 B i t 5 6 B i t 6 7 B i t 7 D i v i s o r L a t c h MSB D i v i s o r L a t c h Access B i t DLAB l B i t D e s c r i p t i o n 0 B i t 0 1 B i t 1 2 B i t 2 3 B i t 3 4 B i t 4 5 B...

Page 55: ...s c r i p t i o n B i t 1 B i t 0 It 0II It 0II F i v e B i t Word Length II 0It II 1II S i x B i t Word Length tI 1 It I t 0 II Seven B i t Word Length II 1II II 1It E i g h t B i t Word Length n o...

Page 56: ...1111 S h i f t Register I d l e 11 0II Data T r a n s f e r From Holding Register Always L o g i c a l 1101 02FE Modem S t a t u s R e g i s t e r B i t 0 1 2 3 D e s c r i p t i o n Delta Clear To Se...

Page 57: ...E r ror 1 P r i n t e r S e l e c t 011 o u t of Paper 01 Acknowledge no II Busy 011 P r i n t e r C o n t r o l L a t c h D e s c r i p t i o n S t r o b e I10 I1 0 Auto F D XT n o n I n i t i a l i...

Page 58: ...Mode 1 S e l e c t s Black And White Mode 0 D i s a b l e s Video S i g n a l 1 E n a b l e s Video S i g n a l 0 D i s a b l e s 640 By 200 B W G r a p h i c s Mode 1 Enables 640 By 200 B W G r a p h...

Page 59: ...e r t i c a l R e t r a c e N o t Used N o t Used N o t Used P a l e t t e Mask 0 Palette Mask 1 P a l e t t e Mask 2 P a l e t t e Mask 3 Border B l u e B o r d e r Green B o r d e r Red B o r d e r...

Page 60: ...2 K 1 0 03EO 03EF R e s e r v e d 0 3F0 N o t U s e d 0 3F1 D r i v e Select S w i t c h B i t 0 N o t U s e d B i t 1 1 DSO DSO 0 DSO D S 1 B i t 2 N o t U s e d B i t 3 Mux FDCDMATC W r i t e O n l...

Page 61: ...LSB F i r s t B i t S e n t S e r i a l l y 1 B i t 1 2 B i t 2 3 B i t 3 4 B i t 4 5 B i t 5 6 B i t 6 7 B i t 7 MSB 0 3F8 0 3F8 Read R e c e i v e r B u f f e r R e g i s t e r C h a r a c t e r Re...

Page 62: ...s m i t t e r Holding Register I n t 2 1 1 E n a b l e s R e c e i v e L i n e S t a t u s I n t e r r u p t 3 1 E n a b l e s t h e Modem S t a t u s I n t e r r u p t 4 7 Always L o g i c a l 0 I n...

Page 63: ...t c h Access B i t Enable 111n n l n 03FC B i t D e s c r i p t i o n 0 11 Data Terminal Ready S e t DTR 1 Request To Send RTS 2 Out 1 3 o u t 2 4 LOOP 5 7 Always L o g i c a l llOgl 1 1 0II Data Term...

Page 64: ...DDSR 2 T r a i l i n g Edge Ring I n d i c a t o r 3 Delta Received L i n e S i g n a l Detect I f B i t 0 1 2 1 On 0 Off or 3 is set t o a l modem s t a t u s i n t e r r u p t i s g e n e r a t e d...

Page 65: ...1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 1 1 Memory S t a r t 0 0000 2 0000 4 0000 6 0000 8 0000 B 0000 0 0000 2 0000 4 0000 6 0000 B 8000 Memory Length 128K 128K 128K 128K 128K 128K 256K 256K 256K 256K 256K Me...

Page 66: ...t s f o r IOCHRDY 1 t o start W r i t e Strobe 1 N o r m a l 8 2 3 7 A 5 W r i t e Strobe G e n e r a t i o n WRITE READ I n t e r n a l V i d e o W a i t States 0 0 w a i t states 1 1 w a i t states...

Page 67: ...EFFFF EOO 00 EFFFF EO 000 EFFFF EO 000 EFFFF 0000 EFFFF EO000 EFFFF 19 18 17 16 4 3 2 1 0 O 1 1 1 1 1 x x x x x 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 0 0 1 1 0 0...

Page 68: ...5 SMD R1206 RESISTOR 1 2K OHM 1 8 W 5 SMD R1206 RESISTOR 2 2K OHM 1 8 W 5 SMD R1206 RESISTOR 3 3K OHM 1 8 W 5 SMD R1206 J3 POWER J 2 FLOPPY J5 9 J 1 0 SERIAL J11 VIDEO J1 5 4 JOYSTK R 1 1 1 4 1 6 2 2...

Page 69: ...uf 16V ELECT RAD 20 CAP 22 UF 25V ELECT RAD 20 CAP 47 uf 16V ELECT RAD 20 CAP 33 pf 10 50V SMD C0805 DESIGNAT0R R1 4 5 17 33 R6 7 8 9 10 12 13 15 18A 19 R26 31 38 40 46 R30 45 R43 44 RP3 RP8 RP4 RP7 R...

Page 70: ...85 88 90 92 99 100 103 105 106 109 110 112 125 C104 107 108 Y1 Y2 u33 U14 u5 u22 U13A u45 U38 u44 u39 U42 43 U26 U41 FB1 10 VR1 VR2 CF1 5 CR1 DIAWA MF DIAWA MF GENfRIC U I1 I I MOTOROLA GENERIC n I1...

Page 71: ...256K X 8 2MEG B I T ROM ODD 2 0 0 N S I C PAL 16R4A E2 E3 U17 U25 U 6 7 8 9 U 1 0 1 5 1 9 2 3 2 7 3 1 3 4 3 6 U26 U29 U41 U40 U18 U30 u12 HUl HU2 su3 s u 4 U13B VENDOR PART NUMBER 8 8 5 9 0 2 4 GENERI...

Page 72: ...HM R10 13 18 19 1 8W 5 SMD R1206 20 22 24 25 RESISTOR 13K OHM R28 R35 1 8W 5 SMD R1206 RESISTOR 91K OHM R31 1 8W 5 SMD R1206 RESISTOR 300 OHM R37 38 1 8W 5 SMD R1206 RESISTOR 1 MEG R11 12 15 16 1 8W 5...

Page 73: ...ONE JACK PHON0 JACK POT 10K DESIGNATOR c 2 0 2 1 C42 C 2 7 3 4 C1 19 28 31 22 25 32 37 u1 u3 u 2 u 4 FB1 9 VR1 s1 J 6 J8 R40 VENDOR GENERIC FAIRRITE 2743002121 MOTOROLA MC78L05 FAIRCHILD UA78L05 TEXAS...

Page 74: ...I I I I I I I I TANDY CORP MADE IN USA 170038Lf REV B PIN 8709867 S A 8859110 AUDM RESET I O J 0 0...

Page 75: ...I I I I I I I e I...

Page 76: ...I I I I i I l r m I I 1 m...

Page 77: ...ARALLEL PRINTER PORT 500 CHAR SEC MAX FLOPPY DISK CONTROLLER CLOCK 16 MHZ FLOPPY DATA RATE 250 KBITS SEC MAX KEYBOARD DATA RATE 50 KBITS SEC MAX POWER SUPPLY SWITCHING RATE 20 90 KHZ CRYSTAL CONTROLLE...

Page 78: ...41 6 4 1 3 I b w 4 L J m L s 4 1 3 4 p W 34 5 6 7 5 6 7 5 6 7 CPU...

Page 79: ...AO 19 ADO 15 a 2 m s 2 ADO 15 HAO HA7 I I I I P m 2 w 2 H 2 H Z B H I I I I l l I I ROH DRAM 4 3 t 2 I 1...

Page 80: ...91 2 m 2 I m 2 81 2 m 2 81 2 m 2 m 2 91 2 0 rn TANDY VIDEO I1 m 7 m s m 2 m 6 VIDEO I C 8000302 I E 4 4 I 3 t 2 I 1...

Page 81: ...I p 1 2 w 2 n p1 2 1 r lk 1 SYSTEM I O...

Page 82: ...I 1 I 2 1 4 3 sH 5 sH 4 sH 2 sH 2 91 2 91 2 sH 2 sH 2 m 2 PSSJ U40 1 0 tinQ I I I 1 I 3 2 1 I 4...

Page 83: ...91 2 91 4 91 2 91 2 91 2 91 2 91 2 91 2 91 2 91 2 91 2 91 3 91 2 91 2 91 2 91 4 111 1 BUS CONNECTORS C 8000302 1 a 3 7 i 4 1 3 1 2 1 1...

Page 84: ......

Page 85: ...I I J i u l f uz m F Q w u l f U B uzs 1 b I r i DUG NO 17ooJ18 REV B LAYERNAK SILKSCREEN LAYER M DATE 8 1 88 I I I I...

Page 86: ...I DUG ND 1 REV B LAYER N A M COM ONENT SIDE LAYER ND 1 DATE 8 1 88 I I I I...

Page 87: ...I I DWG M 1788578 REV B LAYERNAPE GN pLAFE LAYERM 2 DATE 8 1 8 8 I I I I...

Page 88: ...I I DUG M 1900J78 REV 8 LAYER NAME 5V R A M LAYER No 3 DATE 8 1 88 I I I...

Page 89: ...I I DUG NO 1700378 REV 8 L A Y E R NAME SOLDER SIDE L A Y E R NO Lt D A T E 8 1 80 I I I I...

Page 90: ...Devices...

Page 91: ...TANDY BUFFER BLUE CUSTOM IC PART 8079024...

Page 92: ...s i v e p r o p e r t y of Tandy C o r p o r a t i o n N o r e p r o d u c t i o n of any kind may b e made w i t h o u t t h e e x p r e s s w r i t t e n a u t h o r i z a t i o n o f Tandy C o r p...

Page 93: ...Table Of Contents BUFFER BLUE PRELIMINARY SPECIFICATION 1 0 GENERAL 2 0 PIN LIST 3 0 ABSOLUTE MAXIMUM RATINGS 4 0 D C ELECTRICAL CHARACTERISTICS 5 O AC CHARACTERISTICS...

Page 94: ...LIST PIN NAME QW vcc GND 4 4 ADO AD15 16 ADR16 ADR19 4 so s2 3 BHEB 1 RQ GTB 1 READY 1 RESET 1 I o B i d i r B i d i r I n p u t s I n p u t B i d i r o u t p u t o u t p u t DESCRIPTION Power i n p...

Page 95: ...r o l l i n e IOWB 1 o u t p u t CPU DMA 1 0 W r i t e s i g n a l a c t i v e low System c o n t r o l l i n e MEMRB 1 o u t p u t CPU DMA Memory Read s i g n a l a c t i v e low System c o n t r o l...

Page 96: ...ory d e v i c e s O u t p u t s Memory write e n a b l e s i g n a l a c t i v e low Intended t o d r i v e 1 0 M O S memory d e v i c e s O u t p u t s Memory Row Address S t r o b e s a c t i v e lo...

Page 97: ...IPTION 1 0 or Rom p a g i n g d e c o d e s depending upon whether a memory or 1 0 c y c l e is i n p r o g r e s s NMI from 1 0 Bus N M I from 8087 C o p r o c e s s o r NMI t o CPU R e f r e s h r e...

Page 98: ...n i t s 2 mA 0 4 v o l t s DC 1 mA 2 4 v o l t s DC 160 PF Min Typ Max U n i t s 8 mA 0 4 v o l t s DC 1 mA 2 4 v o l t s DC 160 PF 4 6 MEMRB MEMWB I O R B IOWB BUSALE HLDA BHE AO Al9 IODO IOD7 REFRES...

Page 99: ...TIMING DIAGRAMS FIGURE 1 CPUCLK I e tcyc I I I I tLOW I I VOH 4 0V I I I I I I I I I I VOL 0 4V I I I I I t H I I I I I I 1 I I t R I I I I t F FIGURE 2 RESET 1 CPUCLK RSTINB RESET I I I I 6...

Page 100: ...I I CPUCLK OUTPUT I I t2 I I I I I I I I RDYIN I FALSE I 1 t3 I I I I INPUT I I t 4 I READY I I OUTPUT I T3 TW I I I CPUCLK I I I I OUTPUT I I I t5 I I I I t 6 I I tCH RDYIN TRUE INPUT I I I I I I I...

Page 101: ...FIGURE 4 CONTROL GENERATOR I I I t 7 I ALE I I I I I IOW MEMW IOR M E M R INTAB II t 6 t8 l I 8...

Page 102: ...I can overlap and be seen 7 I o u t p u t I I I as o n e pulse by t h e I t 4 I I I I c i r c u i t I I RQ GTB ACKNOWLEDGE f r o m CPU i n p u t 1 t 6 I I I HLDA FIGURE 5B ARBITTER RELEASE CPUCLK e x...

Page 103: ...10 min ADDRESS SETUP TO RAS 25 n s ROW ADDRESS HOLD TIME 17 n s RAS WIDTH 150 n s COLUMN ADDRESS S E T U P TIME 29 n s RAS TO CAS TIME 73 n s WE TO CAS S E T U P TIME 29 n s COLUMN ADDRESS HOLD TIME 4...

Page 104: ...N 4 2 P I N 43 P I N 4 4 P I N 4 5 P I N 4 6 P I N 47 P I N 4 8 P I N 49 P I N 50 OSC24M T R E S E T RDYIN R S T I N B IOCHCKB DACKlB FDDMACKB DACK3B A 0 A 1 A 2 A 3 A4 A 5 vss VDD A 6 A7 A 8 A 9 A 1...

Page 105: ...8 Al5 I n t e r n a l F l i p F l o p 0 Read AO A7 I n t e r n a l F l i p F l o p 1 Read A8 Al5 IOR 0 Channel 1 C u r r e n t A d d r e s s DMA C o n t r o l l e r IOW 0 Channel 1 Base and C u r r e...

Page 106: ...Command R e g i s t e r D e s c r i p t i o n 0 Memory t o Memory Disable 1 Memory t o Memory Enable 0 Channel 0 Address Hold Disable 1 Channel 0 Address Hold Enable X I f b i t 0 0 0 C o n t r o l l...

Page 107: ...s e t r e q u e s t b i t 1 S e t r e q u e s t b i t Don t Care IOR 0 I l l e g a l DMA C o n t r o l l e r IOW 0 Write S i n g l e Mask R e g i s t e r D e s c r i p t i o n B i t l B i t O 0 0 S e...

Page 108: ...i t 6 0 0 Demand mode s e l e c t 0 1 Single mode s e l e c t 1 0 Block mode s e l e c t 1 1 Cascade mode s e l e c t IOR 0 I l l e g a l DMA Controller I O W 0 Clear Byte Pointer Flip Flop IOR 0 I l...

Page 109: ...3 DMA C h 2 A d d r e s s A19 4 7 N o t U s e d PORT 82 WRITE ONLY B i t D e s c r i pt ion 0 DMA Ch 3 A d d r e s s A16 1 DMA C h 3 A d d r e s s A 1 7 2 DMA C h 3 A d d r e s s A18 3 DMA C h 3 A d d...

Page 110: ...obe for DMA cycle 1 No E a r l y Write Strobe for DMA cycle B I T 6 0 Z e r o W a i t States for 1 6 B i t V i d e o 1 O n e W a i t State for 1 6 B i t V i d e o B I T 7 Must be 0 w h e n OSCIN is eq...

Page 111: ...0 0 1 1 0 0 E0000 EFFFF 1 1 1 0 0 1 0 1 1 E0000 EFFFF 1 1 1 0 0 1 0 1 0 E0000 EFFFF 1 1 1 0 0 1 0 0 1 E0000 EFFFF 1 1 1 0 0 1 0 0 0 E0000 EFFFF 1 1 1 0 0 0 1 1 1 E0000 EFFFF 1 1 1 0 0 0 1 1 0 E0000 EF...

Page 112: ...designedto improvesystem performanceby allowingexternal devicesto directly transfer information from the system memory Memory to memory transfer capability is also provided The 8237A offers a wide va...

Page 113: ...hannel DACKwill acknowledge the recognitionof DREQsignal Polarityof DREQis programmable Resetinitializesthese linesto active high DREQ mustbe maintaineduntilthe correspondingDACKgoes active DATABUSThe...

Page 114: ...ressthe registerto be loadedor read Inthe Activecycletheyareoutputsandprovidethe lower4 bitsof the outputaddress si nal ADDRESS Thefour mostsignificantaddresslinesarethree state outputsandprovide4 bit...

Page 115: ...tate of a DMA service The 8237A has requesteda hold but the processor has not yet returned an acknowledge The 8237A may still be programmeduntil it receives HLDA from the CPU An acknowledgefrom the CP...

Page 116: ...eed only be held active until DACK becomes active Again an Autoinitializationwill occur at the end of the service if the channel has been programmedfor it Demand Transfer Mode In Demand Transfer modet...

Page 117: ...t inthe normalmanner The channel 1 cur rent Word Count is decremented When the word count of channel 1 goesto FFFFH a TC is generat ed causingan Channel0 may be programmedto retain the same addressfor...

Page 118: ...ve bit bytes It may also be reinitializedby an Autoinitialize back to its ori inal value Autoinitialize takes place only after an Current Word Reglster Each channel has a 16 bit CurrentWord Count regi...

Page 119: ...alsoset by a Reset This disables all DMA requests until a clear Mask registerinstructionallowsthem to occur The instructionto separately set or clear the mask bits is similar in form to that usedwith...

Page 120: ...t Software Commands These are additional spe cial software commands which can be executed in the ProgramCondition They do not dependon any specific bit patternon the data bus The three soft ware comma...

Page 121: ...ead 0 0 1 0 1 0 0 0 AO A7 BaseandCurrentWordCount Write 0 1 0 0 1 0 1 0 WO W7 CurrentWord Count Read 0 0 1 0 1 0 1 0 WO W7 3 BaseandCurrentAddress Write 0 1 0 0 1 1 0 0 AO A7 CurrentAddress Read 0 0 1...

Page 122: ...done even if some channelsare unused An invalidmode may force all control signalsto go active at the same time APPLICATIONINFORMATION Note 1 Figure8 shows a convenientmethodfor configuring a DMA syste...

Page 123: ...lute maximum rating condtions for ABSOLUTE MAXIMUM RATINGS Ambient Temperatureunder Bias O Cto 70 C CaseTemperature O Cto 75 C storage Temperature 650c to 5ooc Voltage on Any Pin with Power Dissipatio...

Page 124: ...R TDCTW CLK CycleTime 320 250 200 tlS CLK HIGHt o m or LOWDelay Note3 270 200 190 ns HIGHfromCLK HIGH 270 210 190 ns S4 DelayTime Note3 HIGHfromCLK HIGH 200 150 130 ns T W 1 TW2 TEPS TEPW TFAAB ITFAC...

Page 125: ...esistor connected from HRO to V a 5 Output Loadingon the Data Bus is 1 TTL Gate plus 100 pF capacitance is an n collectoroutput This parameterassumes the presence of a 2 2K pullup to Vm or hAEMR pulse...

Page 126: ...to program or examine the controller must be timed to allow at least 600 ns for the 8237A at least 500 ns for the 8237A 4 and at least 400 ns for the 8237A 5 as recovery time between active read or w...

Page 127: ...WAVEFORMS Continued DMA TRANSFER TIMING 2 249...

Page 128: ...w WAVEFORMS Continued MEMORY TO MEMORYTRANSFER TIMING 231466 16 Figure 12 Memory to MemoryTransfer EADYTIMING I I I aw I w I 84 I READY I 231466 17 Figure13 Ready 2 250...

Page 129: ...0237A Tl SlD c TRSTW WAVEFORMS Continued OMPRESSEDTRANSFER TIMING CLK I l l I 1 I A 0 4 7 VALID mw lRllw TRS READY TAM T11 m EOP W EOP 231488 18 Figure14 CompressedTransfer RESET TlMlNG 2 251...

Page 130: ...ISION REVIEW The following list represents key differences be tween this and the 002 data sheet Please review this summary carefully 1 Major cleanup on the NOTE sections of this data sheet a Pin 5 no...

Page 131: ...ion contained h e r e i n is e x c l u s i v e property o f Tandy Corporation N o reproduction of any kind may be made without t h e e x p r e s s w r i t t e n a u t h o r i z a t i o n of Tandy Corp...

Page 132: ...64 P l a n a r C o n t r o l A B C P o r t n o t used 0065 P l a n a r R e g i s t e r Read Write 037C N o n v o l a t i l e memory write o n l y 03F1 FDC Mode C o n t r o l 03F2 FDC D i g i t a l Out...

Page 133: ...n a l 8255A l o g i c Keyboard I n t e r f a c e Logic T h i s s e c t i o n of t h e KFIT custom i n t e g r a t e d c i r c u i t is d e s i g n t o s u p p o r t Tandy 1000 keyboard or Tandy 1 0 1...

Page 134: ...e r r u p t i n d i v i d u a l r e q u e s t mask and programmable i n t e r r u p t modes T h i s c i r c u i t g e n e r a t e s INTR o u t p u t s i g n a l f o r t h e CPU I n a d d i t i o n t...

Page 135: ...BLOCK DIAGRAM I I IR02 IR07 INTAB SA0 SAI SA2 U A B C IMIB I M B NOW1 cOLB mN PIAcm OCB FDWWW FDICKIB F a M L I FWAEI FOOIRI SHARING UmESs DECrnIN6 LOGIC KEYBOAm D O 4 7 REFFEO 3...

Page 136: ...SA 1 SA2 SA7 A B C IOWB IORB 1 4 1 5 1 6 1 7 1 9 20 2 1 22 28 29 30 3 1 32 33 34 37 36 Data bus 0 Data bus 1 Data bus 2 Data b u s 3 Data b u s 4 Data b u s 5 Data b u s 6 Data bus 07 System a d d r e...

Page 137: ...DS2B 8ma 55 27 DCB 38 0 Pr ogr ammable Per iphera 1 I n t e r f a c e Timer output s i g n a l f o r sound generator I O Input d a t a s i g n a l from keyboard In t h e IBM PC keyboard t h i s p i n...

Page 138: ...u t s i g n a l when is HIGH Floppy d i s k motor ON o u t p u t s i g n a l when is LOW Head select i n p u t s i g n a l from f l o p p y d i s k c o n t r o l l e r Head select i n p u t s i g n a...

Page 139: ...up S O T Pull up S oT Pull up S T Pull up 3 s t a t e Pull up S T Pull up Floppy d i s k s e r v i c e r e q u e s t i n p u t s i g n a l t o DMA when is LOW Floppy d i s k s e r v i c e r equest o...

Page 140: ...8 67 0 I 0 I n t e r r u p t r e q u e s t s i g n a l T h i s s i g n a l is used t o i n t e r r u p t t h e CPU when H I G H Real t i m e clock i n t e r r u p t s i g n a l from t h e Real Time C...

Page 141: ...1 35 52 1 8 62 63 64 65 Power s u p p l y 5V Power s u p p l y 5V Ground Ground Notes O C Open Collector 3 S t a t e T r i S t a t e S T S c h m i t t T r i g g e r Max 1 6mal Min O 4ma s i n k i n g...

Page 142: ...ange Hex 0020 0027 0040 0047 OOCO OOC7 0060 0067 0065 03FO 03F7 0200 0207 0378 037F 0 37C 03F8 03FF FFE8 FFEF F u n c t i o n I n t e r r u p t s Timer Sound PPI P l a n a r R e g i s t e r J o y s t...

Page 143: ...t A B i t 0061 P o r t B Description Keyboard Read Data Input Read only Keyboard b i t 0 LSB Read only Keyboard b i t 1 Read only Keyboard b i t 2 Read only Keyboard b i t 3 Read only Keyboard b i t 4...

Page 144: ...used R W O slow speed Read NOVDI Read o u t p u t Timer 2 Read O color Read l P a r i t y check P o r t n o t used Planar R e g i s t e r Read Write R eser ved Reserved Reserved 1 FDC c h i p select e...

Page 145: ...Output Register DOR Write Only D S O DS1 D S 2 Write 0 l o write 0 0 1 Write FDC r e s e t Write Enable DMA Req Int Write Drive 0 Motor ON Write Drive 1 Motor ON N o t used N o t used N o t used FDC...

Page 146: ...l Real Time C l o c k I n t e r r u p t Write l E n a b l e Real Time clock I n t e r r u p t Read Keyboard S e l e c t O Tandy Keyboard 1 101 Enhanced Keyboard Summary on t h e a c t i v e f l o a t...

Page 147: ...ELECTRICAL SPECIFICATIONS 15...

Page 148: ...KEYBOARD TIMING SPECIFICATIONS 1 6...

Page 149: ...I O Write C y c l e Address Cs X X l l I I IOWB 1 0 Read C y c l e Address Cs X X l l I I IORB D a t a 17...

Page 150: ...la I I I 2 IOWB I 3 I I 4 I I I 1 I D a t a X x 5 1 I 6 1 I PROGRAMMABLE INTERRUPT TIMING AND DESCRIPTIONS Must meet I n t e l 8 2 5 9 A A n y differences m u s t be specified PROGRAMMABLE TIMER TIMIN...

Page 151: ...tem address 0 System address 2 I O Write 1 0 Read FDC Port 03FO 03F8 hex Keyboard Port 0060 0067 Read FDC Port 03F7 hex Write FDC Port 03F7 hex Write DORLTCH Port 03F2 P o r t 0062 or C Port 0 0 6 1 o...

Page 152: ...JACKSBORO SPECIFICATION jmp 05 26 88...

Page 153: ...r a B i t of D i v i s i o n by e a c h c h a n n e l 6 2 S y n c h r o n i z a t i o n o f f r e q u e n c y d i v i d e r s 6 3 Minimum W a i t S t a t e G e n e r a t i o n 7 0 S o f t w a r e S p...

Page 154: ...ck s i g n a l i n p u t 14 31313 MHz 50 d u t y c y c l e TTL i n Clock s i g n a l i n p u t e i t h e r 24 MHz or 1 8432 MHz 50 d u t y c y c l e IODO IOD7 14 15 16 17 DS1218 E i g h t b i t p e r...

Page 155: ...t Data acknowledge for DMA ops Sound c h i p wait o u t p u t open d r a i n 24 2 mA OD 60 61 62 63 DS1218 DS1218 D i g i t a l j o y s t i c k p o s i t i o n i n p u t 64 65 66 67 D i g i t a l j o...

Page 156: ...p u t RS232 d a t a t e r m i n a l r e a d y o u t p u t RTS 33 2 mA RS232 r e q u e s t t o s e n d o u t p u t o u t p u t RS232 r i n g i n d i c a t o r i n p u t RS232 t r a n s m i t d a t a 3...

Page 157: ...CTERISTICS 4 1 Inputs Leakage current Min Typ Max Units Vih TTL in Vih DS1218 Vi1 Input capacitance lo uA 2 0 Vcc 5 volts DC 2 1 Vcc 5 volts DC 0 5 0 8 volts DC 10 PF 4 2 PDO PD7 INIT AFXT STROBE Min...

Page 158: ...4 5 IODO IOD7 Io1 vo 1 Ioh Voh Capacitive load M in Typ Max U n i t s 8 mA 0 4 v o l t s DC 2 mA 2 4 v o l t s DC 1 0 0 PF 5...

Page 159: ...u Data S e t u p W r i t e Tdacc Data Access R e a d Tdhr Data Hold R e a d Tdhw D a t a Hold W r i t e Min Typ Max U n i t s 15 30 120 125 65 1 0 30 25 100 nSec nSec nSec nSec nSec nSec nSec nSec Add...

Page 160: ...a d i v i d e r w i l l be enabled 6 2 Synchronization of frequency d i v i d e r s The c u r r e n t 76496 d e s i g n l o a d s each d i v i d e r when i n i t i a l l y w r i t t e n t o with no p...

Page 161: ...ed DMA Enabled for SA DA R W 1 DMA i n t e r r u p t c l e a r DMA i n t e r r u p t h e l d clear DMA i n t e r r u p t allowed DMA I n t e r r u p t e n a b l e DMA EOP i n t e r r u p t d i s a b l...

Page 162: ...L low then back high P o r t C5 Write w s 1 wso Where w s1 0 0 1 1 P W 2 0 0 0 0 1 1 1 1 P o r t C5 Read r e s r e s res Pw2 PW1 P W O w s o Waveshape select b i t s P u l s e Ramp 0 1 1 Reserved 0 T...

Page 163: ...p down t o 27 3 Hz Obviously t h e b i t programming order of t h e frequency is d i f f e r e n t The a c t u a l frequency w i l l be 111 86 KHz divided by t h e number programmed i n t o t h e soun...

Page 164: ...i t s a r e a l l enabled s e t high on reset and must be c l e a r e d by software t o d i s a b l e t h e a p p r o p r i a t e f u n c t i o n The p r i n t e r o u t p u t enable f u n c t i o n...

Page 165: ...i p E n a b l e 0065 R W 1 4 7 P l a n a r C o n t r o l OOCO OOC3 W a11 Sound C h i p Data OOC4 OOC7 R W a11 DAC F u n c t i o n s 020 0 0207 R W a11 J o y s t i c k F u n c t i o n 0378 037A R W a11...

Page 166: ...TANDY COMPUTER PRODUCTS Floppy Disk Support Chip Specification...

Page 167: ...PRODUCTS Floppy Disk Support Chip Specification Content8 Section General Description Pin Description Block Diagram Environmental Specifications DC Electrical Specifications AC Characteristics Timing...

Page 168: ...t h e 765 Floppy D i s k C o n t r o l l e r Generates t h e w r i t e c l o c k t o t h e Floppy Disk Generates s t e p pulses t r a c k 0 indicator DMA request and FDC i n t e r r u p t signals 1 2...

Page 169: ...0 period 2 us 250 ns pulse If SWITCH 1 period 1 us 250 ns pulse If SWITCH 0 then CLK16M 4 If SWITCH 1 then CLK16M 2 Serial data from FDD Serial data from FDC Read Data Window Step pulses to move head...

Page 170: ...COMPUTER PRODUCTS PS8 PS1 D A T A Fer erlRO CONTROL aL O G I C CI K16M SAI TCH U m r I FI T TRO FDCCl K C L O C K S ACK ROOATA BLOCK OI flGRF1H RDD RDW DATH S E P A R A T O R 3 I W L 1 CONTROL L O G I...

Page 171: ...ICC Total Power 3 2 3 Leakage Current All Inputs Vin 0 0 v 4 5 5 0 5 5 0 0 0 10 Vin 5 0 v 10 volts volts milli amps milli watts micro YPS micro amps 3 2 4 Input voltages 3 2 4 1 Except RDDATA TRK Log...

Page 172: ...T Timing IH FIH I FIL Dk FIL W C DRQ DRQ FDR DRQL FDRQ F C FD RbH WCK DRQ D I FDRQ Min Typ Max U n i t s 90 120 130 nSec 5 1 0 nSec 100 120 160 nSec 245 250 255 nSec _ 100 250 250 nSec 5 1 0 nSec 2 o...

Page 173: ...RDA RDDH RDD mW R D D RDWBNDI wc RDAS RDWC RDD RDAS RDWC RDDH c RDAS RDWC RDDH Min Typ Max 30 30 30 30 30 30 U n i t s nSec nSec nSec nSec nSec nSec e 200 350 550 nSec 188 313 nSec 240 250 260 nSec 8...

Page 174: ...TANOY COMPUTER PRODUCTS FDSL AC TIMING 1 1 FIG l FDCCLK FIG 2 WCK WCKL WEL FIG 3 WRITE DATA TIMING 9...

Page 175: ...TANDV COMPUTER PRODUCTS I I I FIG 4 DMAlINTERRUPT TIMING 10...

Page 176: ...TANDV COMPUTER PRODUCTS I TRKO I I FLT TKO j I I I I I TL FTHA it 4 b RSL FTL I I FR STP A I I FIG 5 CONTROL LOGIC TIMING 11...

Page 177: ...TANOY COMPUTER PRODUCTS A 4 FRDAL RDDH RDD I 1 I I 1 RDW I I I I R D D H R D W C 4 LRDWc RDDH 1 1 I I I I I j R D W C 4 RDDH FIG 6 DATA SEPARATOR TIMING 12...

Page 178: ...Aor non DMAmode Inthe non DMAmodethe FDC generatesinterruptsto the processorevery time a data byte is to be transferred Inthe DMA mode the proces sor need only load the command into the FDC and all da...

Page 179: ...ut 38 LCTIDIR Lowcurrentdirection 39 R WI SEEK Readlwritelseek output output 40 vcc D C p e r PinFunctions RESET Reset The RESET input placesthe FDC in the idle state It re sets the output lines to th...

Page 180: ...s UnitSelect0 l The US0 and US1 outputs select the floppy disk drive unit PSO P s Preshift0 l ThePSoand PSIoutputs arethe writeprecompensation status for MFM mode They determineearly late and normalti...

Page 181: ...V f 5 crPD765A 7265A andV c c 5V f10 PD765A 2 7265A 2 umm rast k n d r Symbol Mln lyp Mar Unit Condltlonr Inputvoltage VIL 0 5 0 8 V iow Inputvoltage VIH 2 0 Vcc O 5 V high OutputWage VOL 0 45 V IOL...

Page 182: ...m b tAW 0 0 ns Ao E hold time t o m t IWA 0 0 ns WR width h v 250 200 ns Datasetup time t o m t tDW 150 100 ns 5 0 ns INT delay time from mt tRl tWD 500 400 ns Datahold time f r o m m t INTdelay time...

Page 183: ...1 Stepactivetime high tSTP 6 7 8 6 7 8 ps Note4 Stepcycletime tSC 33 Note 2 Note2 33 Note 2 Note2 ps Note4 Faultresetactivetime high F R 8 0 10 8 0 10 ps Note4 Write datawidth WDO 10 50 10 50 ns USo...

Page 184: ...NEC TimingWaveforms cont Clock DMA Operation I 1 FDD WdteOperation 4I t Seek Operation FDD Read operation Glp R dD 1 Wlndav ll0D1Eltherpoiarilydata wlndowiovalid TerminalCount WriteClock 6 9...

Page 185: ...FDD 1Busy DBp DpB FDD 2 Busy DE3 D3B FDDnumber 3 is inthe Seek mode If any of the DnB bits is set FDC will not accept reador write command DB4 CB A Read or Write command is in process FDCwill not acc...

Page 186: ...Status Reoitter 1Icontl Dp ND During execution of Read Data Write De leted Data or Scan command if the FDC cannot find the sector specified in the No Data IDR 2 Register this flag is set Duringexecut...

Page 187: ...andSymbol Description table A0 Address Line 0 C Cylinder Number D IData written intoa sector A0 controls selection of main status register Ag O or dataregister Ao I track numbers 0 through 76 otthe me...

Page 188: ...rsare readandcom pared US standsfor aselecteddrivenumber0 or 1 USo US UnitSelect Table4 InstructionSet Notes7 2 Read Data Command W MT MF SK 0 0 1 1 0 Commandcodes w X X X X X HD US1 US0 Noie3 w Sectn...

Page 189: ...1 Commandcodes W X X X X X HD US1 US W SectorIDinformationpriwtouwnmandexecutlon The4 bytes w w w w EOT w GPL W DTL aremparedagainst headeronfloppy disk Execution Result R STO Statusinformationanerco...

Page 190: ...yte Execution FDCformatsanentire track Result R STO Statusinformationaltercommandexecution R ST1 R ST2 R R R R Inthiscase the IDinformationhas no meaning Sun Equal Command W MT MF SK 1 0 0 0 1 Command...

Page 191: ...X X X HD US1 US0 w Sector ID informationprior to commandexecution w W W W EDT w GPL w STP Execution Datacomparedbetweenthe FDDand main system Resuit R ST0 Status informationafter commandexecution A S...

Page 192: ...transfer to the pPD765AlpPD7265isrequiredonly inthecommandand resultphases andnotduring the executionphase During the execution phase the main status register neednot be read If thepPD765AIpPD7265is i...

Page 193: ...tus register0 S O Isread afterSense interruptStatus is issued not ready NR will be indicated The polling of the ready line by the pPD765AIpPD7265occurs con tinuouslybetweencommands thus notifyingthe...

Page 194: ...ed data field are not checkedwhen SK 1 During disk data transfers between the FDC and the processor via the data bus the FDC must be serviced by the processorevery 27ps in the FM mode and every 13psin...

Page 195: ...o a l high andterminates the command Statusregister0has bits 7and6 set to 0 and1 respectively ReadID The Read IDcommand is usedto give the presentposi tion of the recording head The FDC stores the val...

Page 196: ...processor DFDD Dprocessor or DFDD Dprocessor The hexidecimal byte of FF either from memory or from FDD can be used as a mask byte be cause it always meets thecondition of the comparison One s compleme...

Page 197: ...ring the execution phase it is in the non busystate While the FDC is inthe non busystate anotherSeek commandmay be issued and in this manner parallel seek operations may be done on up to four drives a...

Page 198: ...for eachof the three internal timers The HUT head unload time definesthe time fromthe endof the executionphaseof one of the ReadlWrite commands to the head unload state This timer is programmablefrom...

Page 199: ...2 GAP4a SYNC FF W reads status register0 it will find an 80H indicating an Invalidcommandwas received A Sense InterruptStatuscommand must besentaftera seek or recalibrate interrupt otherwise the FDC...

Page 200: ...Format Sheet 2 of 2 pPD765A Inaex Formal GAP I IAM I GAP1 I ID GAP2 I D A A I GAP3 I ID 1 1 V SINC 7 WE r 7 I pPD7265A Index Formal IGAP1 I ID I GAP2 I DATA 1 GAP3 I ID I GAP2 I I D J T V SYNC 7 r IO...

Page 201: ...Power Supply...

Page 202: ...loOoSL POWER SUPPLIES SINGLE AND DUAL INPUT...

Page 203: ...lOOOSL 67 WATT SINGLE INPUT POWER SUPPLY CONTENTS BLOCK DIAGRAM THEORY OF OPERATION TROUBLESHOOTING PARTS LIST PCB ART SCHEMATIC...

Page 204: ...DC OUTPUT I FANOUT m c c1 Y z z 0 cl x INPUT AC 120V OR 240V FG 12v 12v RECTIFIER 0 12v t o FILTER SWITCHING DRIVER 240V 0 INTERNAL JUMPER 5v 0 t I I 4 1 DC VOLTAGE FEED BACK A OVER VOLTAGE PROTECTOR...

Page 205: ...stor Q1 is On the Q1 current excites the transformer T1 and voltage rises in the bias coil of Tl 5 6 which leads transistor Q1 positive bias then transistor Q1 turns ON When transistor Q1 turns ON col...

Page 206: ...ble Transformer while monitoring the 5 output with the oscilloscope and DVM Supply should start with approximately 40 60 VAC applied and should regulate when 90 VAC is reached If output has reached 5...

Page 207: ...t h e 5 o u t p u t v o l t a g e rises between 5 8V t o 6 8V a c o n t r o l s i g n a l t u r n s on t h e photo c o u p l e r PHC2 P h o t o T h y r i s t o r w i t h t h e c u r r e n t of zener d...

Page 208: ...o r v a l u e s of loads r e q u i r e d The e n t r y on t h e t a b l e f o r Safe Load Power is t h e minimum power r a t i n g s f o r t h e l o a d resistors used NOTE Because of its d e s i g n...

Page 209: ...d i s c o n n e c t e d check for s h o r t e d r e c t i f i e r s or c a p a c i t o r s Check Over V o l t a g e Protector Read t h e o u t p u t v o l t a g e w i t h a DVM a t t h e 5 o u t p u t...

Page 210: ...SOV DIV 5pS DIV Q1 Collector Waveforms Input 90 VAC Minimum Load 0 5V DIV 5p S DIV Q1 Base Waveforms rnput 90 VAC Minimum Load...

Page 211: ...2 v 7 0 A 0 7 ohms 60 W 2 4A 5ohms 5OW 0 25A 48ohms 5 W MINLOADI LOADR 1 25A 0 15A 0 4 ohms 80ohms 0 Table 1 Load Board Values 67 w a t t ISOLATlON OUTPUTLOADS 5v 1 AC 12v VARIAC L POWER SUPPLY TRANSF...

Page 212: ...nd output voltage are represented by t h e following equations Vo n x Vf V o Output voltage n Turn ratio of t h e transformer T 1 vf Collector Voltage at turn off t i m e Vin x Ton vf x Toff V i n Inp...

Page 213: ...Q1 Collector Waveforms Shorted Secondary Components Input 90 VAC...

Page 214: ...6 W V l0WV l0WV CONNECXIRS SKl Connector 2 conductors Input SK2 Connector 2 conductors FBn out s 3 1 Connector 10 conductors Output SK3 2 Connector 4 conductors Output DIODES D1 Silicon Stack 4OOV M...

Page 215: ...NTED CIRCUIT BOARD PC1 Printed Circuit Board 1 0 5 0 RESISTORS R 1 Thermistor 8 R2 3 Carbon lOOK R 4 Metal oxide 27 R5 6 19 20 Metal oxide 27K 10 56 1 5 0 1 1 0 5A 3 0 d 5 0 d 1 5 0 d XPC 1 6A 1 2w 2...

Page 216: ...4 W 1 4 W 1 4 W 1 6 W 0 5 12A 2A 5A QTY RS Part No 2 1 1 1 Mfr s Part No RSF2BWOohmsJ RD25P5600hplsJ o r RI 25S5600hmJ Adjust 330 75Ooh s RD25P270oWJ or RD25S27OohmsJ Adjust 180 47Oohms RD25P47oh 1 J...

Page 217: ...Power Supply PCB Silkscreen...

Page 218: ...Power Supply PCB Component Side...

Page 219: ...1 AC IN 3 sK1 cd D2 a Dl1 PHC2 RIF A I R16 OND QND 12V 12 Nc l2V QND SV sv sv OND QND OH 1 I s K 2 ZFA model no 8790085...

Page 220: ...lOOoSL 67 WATT DUAL INPUT POWER SUPPLY...

Page 221: ...lOOOSL 67 WATT DUAL INPUT POWER SUPPLY CONTENTS OPERATING CHARACTERISTICS BLOCK DIAGRAM THEORY OF OPERATION TROUBLESHOOTING PARTS LIST PCB ART SCHEMATIC...

Page 222: ...0 15 0 7 0 2 4 0 25 A A A Over Current Protection Current L i m i t ICLl ICL2 I C L 14 0 4 8 1 0 A A A Over Voltage Protection Crowbar 5 8 6 8 V Output Noise Vol v02 V03 mV P P mV P P mV P P 50 100 15...

Page 223: ...DCOUTPUT I FAN OUT m C a Lc z m c1 0 c1 x INPUT AC 120V FG SWLTCHING RECTIFIER DCVOLTAGE FEEDBACK I OVER VOLTAGE L 1 J...

Page 224: ...istor Ql is On the Q1 current excites the transformer T1 and voltage rises in the bias coil of Tl 2 3 which leads transistor Q1 positive bias then transistor Q1 turns ON When transistor Q1 turns ON co...

Page 225: ...p power slowly with the Variable Transformer while monitoring the S output with the oscilloscope and DVM Supply should start with approximately 40 60 80 120 VAC applied and should regulate when 90 180...

Page 226: ...u t p u t v o l t a g e rises between 5 8V t o 6 8V a c o n t r o l s i g n a l t u r n s on t h e photo c o u p l e r PHC2 P h o t o T h y r i s t o r w i t h t h e c u r r e n t of zener diode Dl11...

Page 227: ...robes Load board with connectors See Table 1 for values of loads required The entry on the table for Safe Load Power is the minimum power ratings for the load resistors used NOTE Because of its design...

Page 228: ...each output and with output loads disconnected check for shorted rectifiers or capacitors Check Over Voltage Protector Read the output voltage with a DVM at the 5 output terminals by increasing the in...

Page 229: ...100V DIV Sp s DIV Ql Collector Waveforms Input 90 VAC Minimum Load 0 SV DIV 5p S DIV 01 Base Waveforms Input 90 VAC Minimum Load...

Page 230: ...0 A 0 7 ohms 12V 0 15A 80ohms 5 W 2 4A 5ohms 12 v 0 0 0 0 25A 48ohms Table 1 Load Board Values 67 watt LOAF R 60 W 50 W 5 W ISOLATION VARIAC OUTPUT 1 5v AC 12v ISOLATION OUTPUT 5v AC 12v VARIAC POWER...

Page 231: ...tWaveform The input and output voltage are represented by the following equations Vo n x vf Vo Output voltage n Turn ratio of the transformer T1 Vf Collector Voltage at turn off time Vin x Ton Vf x To...

Page 232: ...100V DIV 5ps DIV Q1 Collector Waveforms Shorted Secondary Components Input 90 VAC...

Page 233: ...K V 5 0 W V 25wv 25wv 16WV l0WV l0WV Connector 2 conductors Input Connector 2 conductors bn out Connector 10 conductors Output Connector 4 conductors Output Pin Terminal Voltage Selector Jumping Conn...

Page 234: ...C2 IC Regulator 12V IC3 IC Regulator 36V P H O T O WUPLER PHCl Photo Coupler 55V PHC2 Photo Coupler 600V PRINTED CIRCUIT BOARD PC1 Printed Circuit Board 1 0 5 0 RESISTOAS Rl hermister 16 R2 3 4 5 Carb...

Page 235: ...4W 1 4U 1 4U 1 4U 1 4W 1 4w 0 5W 6A a 5A QTY RS Part No 1 1 1 1 1 1 1 3 2 2 1 1 1 2 Mfr s Part No RSFZBlOOKohmsJ RSF2BlOOohmsJ RD25P560ohmsJ or RD25S5600hmsJ Adjust 330 68Oohms RD25P330ohmsJ or RD25S3...

Page 236: ...Power Supply PCB Silkscreen...

Page 237: ...I Power Supply PCB Component Side...

Page 238: ...1 AC I N a I D2 I l2OV 0 240V c RL R5 4 L t D3 l 9 R27 C2S P Nc sv fa OH 12v t 1 2 Nc 12v OH 5v 5v sv OM OND 1 x 1 t12V F A N model no 8790084...

Page 239: ...Keyboard...

Page 240: ...N860 4703 T Keyboard assembly The keyboard is encoded in such a way as to produce a unique output code for each key that is pressed and or released The connumication with the host corrputer is a sync...

Page 241: ...5 F a FIGURE 1...

Page 242: ...e keyboard generates a unique Hex scan code d r each keyswitch that is pressed mike code and released break code For the AT M e the break code is the saxe as the make code preceded by F Hex Exarrple T...

Page 243: ...0 3COO 3D00 3EOO 3FOO 4000 4100 4200 4300 4400 e Note 011B 5400 5500 5600 5700 5800 5900 SA00 5B00 5C00 5D00 e Note 011B 5 E O O SF00 6000 6100 6200 6300 6400 6500 6600 6700 7200 46 c 6 Notef Notef El...

Page 244: ...07 87 0736 08 88 0837 09 89 0938 O A 8A OA39 O B 8B OB34 oc 8C OC2D O D 8D OD3D O E 8E OE08 E02AE052 EOD2EOAA 5200 E02AE047 EOC7EOAA 4700 E02AE049 EOC9EOAA 4900 45 c5 Note E035 EBB5 352F 37 B7 372A 4A...

Page 245: ...8 98 186F 19 99 1970 1A 9A 1A5B 1B 9R 1B5D 2B AB 2B5C E02AE053 EOD3EOAA 5300 E02AE04F EOCFEOAA 4FOO E02AE051 EODlEOAA 5100 47 c 7 4700 48 c8 4800 49 c 9 4900 OF00 _____ 1051 1011 1157 1117 1245 1205 1...

Page 246: ...A7 A8 9 c CB cc CD 4E27 Note 1E61 1F73 2064 2166 2267 2368 246A 256B 266C 273B 2827 1COD 4B00 4D00 _ _ 4E2 Note 1E41 lEol 1FS3 1F13 2044 2004 2146 2106 2247 2207 2348 2308 244A 240A 254B 250B 264c 26o...

Page 247: ...Bo 3062 3042 3002 31 B1 316E 314E 310E 32 B2 326D 324D 320D 33 R3 332C 333C 34 B4 3428 343E 35 B5 352F 353F 36 B6 Note Note Note8 E02AE048 EOC8EOAA 4800 4800 4FOO 4F31 7500 4F CF 51 D1 5100 5133 7600...

Page 248: ...Scancode ASCII code u Shift Ctrl ALt EOID EO9D Note Note Note Note E02AE04B EOCBEOAA 4B00 4B00 7300 E02AEOSO EODOEOAA 5000 5000 _____ E024E04D EOCDEOAA 4D00 4000 7400 52 D2 5200 5230 Note 53 D3 5300 5...

Page 249: ...tiated Note4 1NT 1BH is invoked Note5 the numlock active bit is toggled Note6 ALT num pad generates raw ascii code of typed number Note7 the caps lock active bit is toggled Note8 hold shift lock activ...

Page 250: ...g t h e ta l i n e low transmissions are disabled The keyboard w i l l retain the keyccde for the pressed key i n its buffer u n t i l t h e clock and data l i n e s return to the idle state The keybo...

Page 251: ...leven bit data wxd This conmmication is bi directional with the keyboard clocking all data transfers When no comnunications are in progress the data and clock lines are high indicating an idle state K...

Page 252: ...edge of the clock See Figure 3 for timing diagram During the transmission of a data word the keyboard periodically checks the state of the clock line I f the clock l i n e is low during these checks p...

Page 253: ...t system reset ctrl at Delete or by Pwe r on Reset Upon successful carpletion of the Self Test during Paver Reset the keyboard is set to X T mude i f the keyboard detects a low level on the data l i n...

Page 254: ...onds then releasing the clock line after clanping the data line low to indicate a start bit The keyboard will respond with an RTS within 5 microseconds by clocking the start bit into the keyboard The...

Page 255: ...self test routine similar to the Pckler a Reset and is placed in its default state Upon receiving this carmand the keyboard w i l l transnit the last byte of data sent to the host system SEX DEFAULT F...

Page 256: ...with no change to the existing rate or delay parameters The new ccpnnand is processed and t h e keyboard continues scanning t h e matrix The parameter byte consists of an eight bit word with b i t 7 m...

Page 257: ...5 Rate 1 0 1 0 0 1 4 3 Y 1 0 1 1 5 0 1 0 0 0 0 0 1 30 0 I 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 I O 0 0 0 11 26 7 1 4 0 3 7 3 3 3 0 2 7 1 0 0 0 1 0 1 24 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0...

Page 258: ...present status of the indicators processes the new comnand and starts scanning the matrix The parameter byte is an eight bit word w i t h bits 3 7 always set to low B i t 0 is the Scroll Lock Indicat...

Page 259: ...waits for the parameter byte When the keyboard receives the paramter byte it responds with an Acknmledge Aparamter byte of 00 Hex w i l l cause the keyboard to transmit the Hex value for the Scan Set...

Page 260: ...FO 5F FO 62 FO O E FO 16 FO 1E FO 26 FO 25 FO 2E FO 36 FO 3D FO 3E FO 46 FO 45 FO 4E FO 55 FO 66 FO 67 FO 6E FO 6F FO 76 FO 77 FO 7E FO 84 FO OD FO 1 5 FO 1 D FO 24 FO 2D FO 2c FO 35 FO 3 c FO 43 FO 4...

Page 261: ...FO 64 Fo 65 Fo 6D FO 6C FO 75 Fo 7D Fo 7c Fo 1 4 Fo 1c FO 1B FO 23 FO 2B FO 34 FO 33 I 3B FO 42 FO 4B Fo 4c Fo 52 Fo 5A FO 6B Fo 73 Fo 74 Fo 1 2 Ffl 1 A Fo 22 Fo 21 2A Fo 32 FO 31 E O 3A FO 41 Fo 49...

Page 262: ...amter byte the keyboard sets the selected key to the function selected by the cannand byte and continues to scan the matrix i f it was previously enabled These camrands affect only Scan Set 3 operatio...

Page 263: ...Lock and Scroll Lock These indicators are located in the keytop of each respective key The keyboard will power up with all indicators OFF except when the host system such as the Tan 3000 NL sets them...

Page 264: ...W E B A T I N G O to 50 degrees C N O N O P E R A T I N G 2 0 to 60 degrees C 7 2 RELATIVE HUMIDITY 20 to 90 non condensing 7 3 SHOCK rating and non aperating 10G 11 m S duration 7 4 VIBRATICN rating...

Page 265: ...MEMBRANE I r i I L N07C 1IEY8rJAFtD UNIT ASSt PROPOSAL...

Page 266: ...I I 3 I I 4 I 5 I 6 Buffer Clock I 1 1 1 I I I I I I I I 1 I 2 1 5 61 2 FDXA 4006 5...

Page 267: ...2 0 17 CO1 C 0 2 C 0 3 C 0 4 C 0 5 C 0 6 C 0 7 C 0 8 X 5 0 20 D l 0 F 0 9 F 1 0 Fl1 F 1 2 F 1 3 F 1 5 F 1 6 X9 0 21 E 0 8 E 0 9 E l 0 Ell E l 2 E l 3 D O 8 D O 9 X l l O 23 E l 5 E l 6 F 1 4 COO A 0...

Page 268: ...5 L l 5 3 1 6 1 L O 1 3 0 1 4 0 L 2 L 3 vcc Y O 1 2 3 4 5 5 Y 1 dG U 3 s 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 1 2 3 2 4 2 5 2 6 2 1 1 s 3 0 3 4 2 0 2 L P I 1 P I G Q e 1 1 P 1 2 P l l P L E P L 3 M 1 1 2 2...

Page 269: ...1 I 2 I 3 I 4...

Page 270: ...t 0 input or gate control input for counter0 INT1 3 3 Interrupt 1 input or gate control inputfor counter 1 lU P 3 4 Input to counter0 11 P3 5 Inputto counter 1 WR P3 6 The write control signal latches...

Page 271: ...r r I O l I n s o I O U 1 Y I l V 1 00U 11111...

Page 272: ...RESONATOR X1 T O BE BENT A S ABOVE DRAWING AFTER MOUNTED CAPACITOR C6 T O BE N O T BENT 2 CONNECTORS CNl CNZ CN3 TO B E NOT FLOATED 3 JUMPER WIRE 52 TO BE NOT MOUNTED 4 JUMPER WIRE I S 30 POSITIONS C...

Page 273: ...0 0 0 0 0 0 N86D 4700 RIOI OI HANDA...

Page 274: ...Disk Drive...

Page 275: ...TEAC FD 55BR FR GR M I N I FLEXIBLE DISK DRIVE MAINTENANCE PRWU X...

Page 276: ...r c u i t 224 2 2 2 1 S t r a p c i r c u i t 226 2 2 2 2 F r o n t LED c o n t r o l c i r c u i t 227 2 2 2 3 Head load c o n t r o l c i r c u i t 228 2 2 2 4 Write erase c o n t r o l c i r c u i...

Page 277: ...a c k c o n n e c t o r s 54 a n d 58 3205 3 2 2 5 P r e c a u t i o n s f o r f l a t cable c o n n e c t o r s 5 5 a n d J 7 3207 3 2 3 Head Cable Treatment 3209 3 2 4 I n i t i a l S e t t i n g o...

Page 278: ...Track Alignment 3449 3 4 13 Check and Adjustment of Track 00 Sensor 3460 3 4 14 Check of Track 00 Stopper 3470 3 4 15 Check and Adjustment o f Index B u r s t Timing 3473 3 5 MAINTENANCE PARTS REPLAC...

Page 279: ...SECTION 2 THEORY OF OPERATION 200...

Page 280: ...IDE ONE SELECT WRITE DATA 4 i DRIVE SELECT 0 3 WRITE GATE MOTOR ON STEP C o n t r o l DIRECTION SELECT c i r c u i t I N USE HEAD LOAD TRACK 00 INDEX WRITE READY PROTECT DC POWER 4 Head load solenoid...

Page 281: ...r c u i t boards The frame i s made o f aluminum d i e c a s t t o maintain t h e s t a b i l i t y o f t h e FDD i n s t r e n g t h p r e c i s i o n d u r a b i l i t y and expansion c o e f f i c...

Page 282: ...rite core Read write gap Fig 202 External view of magnetic head core The magnetic head assembly head carriage Ass y of t h i s FDD has two heads One i s f o r s i d e 1 surface of t h e d i s k and t...

Page 283: ...d between two heads The side 0 surface of the head and the disk are s e t t o nearly the same height and the depression of the side 1 head produces the stable contact between the heads and the disk Th...

Page 284: ...ess of design so t h a t they a r e mutually o f f s e t with the expansion of t h e disk To improve t h e continuity 7 Detection mechanisms a F i l e p r o t e c t detection mechanism This mechanism...

Page 285: ...t u r n i n g o p e r a t i o n t o t h e t r a c k 001 it i s r e q u i r e d t o i n p u t t h e s t e p o u t command w i t h s e v e r a l a d d i t i o n a l steps t o t h e maximum t r a c k nu...

Page 286: ...c u i t and control c i r c u i t a r e mounted on the PCBA MFD control main PCBA and servo c i r c u i t i s on the PCBA DD motor servo 2 2 1 Read Write Circuit The read w r i t e c i r c u i t i s c...

Page 287: ...Fig 203 Block diagramof LOV PASS F I L T E R SWITCH F I L T E R read write circuit I N 0 Q I O b 1 1 Jl 22 CFI...

Page 288: ...state of the switch f i l t e r and the cut off frequency of the low pass f i l t e r i s s e t t o low l e v e l the switch f i l t e r capacitors 2 Write current switch W r i t e current switch is...

Page 289: ...e t r a c k p o s i t i o n SFO SF1 s i g n a l s I Models and t r a c k p o s i t i o n 1 T r 0 0 2 1 T r 2 2 3 9 Tr 00 43 Tr 44 79 Y T H L H Switch f i l t e r Write c u r r e n t s w C u r r e n t...

Page 290: ...of 230 times approx The pre amp output i s supplied t o the d i f f e r e n t i a t i o n amplifier via the low pass f i l t e r and the switch f i l t e r t o eliminate undesirable high frequency noi...

Page 291: ...TP41 Pre amp output TP5 Differentiation amp output TP7 Differentiation amp output TP8 Peak detector output in U2 RD B F models lus approx G model O 5pslapprox READ DATA J1 30 U u u u Fig 204 Read ampl...

Page 292: ...ration COMO COMl SIDE 0 read operation 2 7V ov SIDE 0 write operation 11 5v ov SIDE 0 write operation I 11 5V I ov SIDE 1 read operation I ov I 2 7v SIDE 1 write operation ov 11 5V SIDE 1 write operat...

Page 293: ...ning on and off the two write drivers alternately I Erase on Erase off delay delay 1 WRITE GATE 51 24 WG U2 29 EG TP2 WRITE DATA 51 22 Write data latch in U2 I L I I I l u u 1 Write driver output n n...

Page 294: ...i n h i b i t the operation of the common d r i v e r write d r i v e r erase d r i v e r and write control l o g i c i n the LSI which p r o t e c t the disk from the erroneous w r i t e o r erroneou...

Page 295: ...0 read 2 7V approx Side 1 write OV approx Side 0 write Side 1 read OV approx b Rwol pin 13 RWll pin 15 Terminals for side 1 head connection 1 11 5V approx WRITE DATA interval Side 1 read 2 7V approx S...

Page 296: ...ox 2 7 V I approx Read 2 D i f f e r e n t i a t i o n amplifier Write a DIFI pin 5 pin 4 D i f f e r e n t i a l input terminals t o the d i f f e r e n t i a t i o n amplifier The phase of pin 5 and...

Page 297: ...prox Read d C I pin 43 pin 43 Write D i f f e r e n t i a l input terminal of the comparator peak d e t e c t o r The phase of pin 43 and 42 a r e opposite each o t h e r 2 5V approx 2 5V approx Read...

Page 298: ...pin 2 2 Output terminals of the erase d r i v e r which is constructed with open c o l l e c t o r NPN t r a n s i s t o r s Two terminals a r e equipped While the EG input terminal i s HIGH l e v e...

Page 299: ...a t write operation These terminals a r e a l s o used f o r the asymmetry adjustment a t read operation 11V approx 12V approx Write Read e CD pin 36 In order t o p r o t e c t the head from undesira...

Page 300: ...n p u t t e r m i n a l s f o r w r i t e permit WG and erase p e r m i t EG from t h e c o n t r o l c i r c u i t i n t h e FDD Refer t o T a b l e s 202 and 203 5 Others a p i n 31 Schmitt TTL i n...

Page 301: ...and DGND p i n 38 OV p o w e r terminals mainly f o r t h e following c i r c u i t s i n t h e LSI AGND Analog operation c i r c u i t s such a s pre amplifier EGND Erase d r i v e r X N D D i g i t...

Page 302: ...O Z Z Z 0 L Logic l e v e l 0 LOW R COM voltage 2 7 V approx H Logic l e v e l 1 HIGH P Positive pulse Z High impedance OPEN N Negative pulse Hi COM voltage 1 1 5 V approx F FALSE No pulse output LV...

Page 303: ...c u i t write erase control c i r c u i t motor on gate ready detector stepping motor control c i r c u i t track counter RD INDEX gate interface driver e t c Almost a l l the c i r c u i t s except...

Page 304: ...I N N I n I EA0 L0AD SOLENOI D TO FROY READ fiRlTE CIPCUlT 5 PCBA FRONT OPT 5 STEPPING dOTOR...

Page 305: ...e equipped Refer t o the Specification items 1 11 and 1 12 a s t o the d e t a i l s of s t r a p function Some m d e l s have not s t r a p posts These models have soldered jumping wires instead of...

Page 306: ...n a l s are g a t e d to o u t p u t a s t h e E D s i g n a l t h r o u g h t h e LED d r i v e r While t h e DLED s i g n a l is L O W l e v e l t h e f r o n t LED t u r n s on Notes 1 s Output s i...

Page 307: ...oid d r i v e r U 3 pin 3 14 While the HLC s i g n a l i s HIGH l e v e l the head load solenoid is a c t i v a t e d Notes PRDY Ready f Pre ready Pre ready I n t e r n a l s i g n a l of LSI I t goes...

Page 308: ...i r c u i t 1 The HOD output s i g n a l is supplied t o the overdrive c i r c u i t 1 constructed by t r a n s i s t o r s 42 NPN and Q1 PNP and it makes Ql t u r n on while the HOD s i g n a l i s...

Page 309: ...HLC signal HOD signal llV approx Applied vol taqe 4V approx to solenoid coil j a v e r 1 approx Fiq 209 Overdrive timing of head load solenoid 230...

Page 310: ...t FPT i n p u t o f LSI LOW The same a s t h a t t h e f i l e p r o t e c t s e n s o r d e t e c t s t h e w r i t e e n a b l e notch l i g h t p a s s i n g c o n d i t i o n o f a d i s k which i...

Page 311: ...a l c u l a t e d value excluding the o s c i l l a t o r tolerance and propagation delay 2 HO and SS input terminals a r e connected t o HD output HD output s t a t e is determined by H D S input s i...

Page 312: ...n t h e f o l l o w i n g c o n d i t i o n s t e r m i n a l i s s u p p l i e d t o MC H s L x L 1 3 3 s d e l a y DISK H Notes MC Motor r o t a t i o n a t HIGH MONO M O T O R ON i n p u t s i g n...

Page 313: ...3 L 461msec d e l a y a f t e r t h e l e v e l change of t h e MC s i g n a l t o TRUE H I G H When t h e o u t p u t s of t h e MON d e l a y 1 and t h e i n t e r n a l ready l a t c h are c o i n...

Page 314: ...ready i n U1 DSEL DRIVE SELECT i n p u t s i g n a l LOW I 443246l m s _c I I MC Motor on command 1 Ready state i n U1 MON d e l a y 2 4 9 5 1 m s o l I I Ready I DSEL i n p u t Ul 53 I I IDXO o u t...

Page 315: ...All the three c i r c u i t s of ready detector a r e r e s e t by the MC signal goint t o FALSE LOW l e v e l 236...

Page 316: ...ectional s h i f t r e g i s t e r and changes the a c t i v a t i n g order of the stepping motor c o i l a s shown i n Fig 211 The latched output i s supplied 2 I n t e r n a l s t e p generator The...

Page 317: ...der t o improve t h e torque margin i n the seek operation p a r t i a l 2 phase drive period i s provided by the phase d r i v e s e l e c t o r only i n the i n i t i a l stage when the d r i v e ph...

Page 318: ...verdrive timer 2 output Coil d r i v e r input P A PB P N A P N B 48tpi I n t e r n a l s t e p gen in U1 SOD 0verdrive t i m e r 2 Coil d r i v e r input output PA PB P N B P N B tl I n t e r n a l s...

Page 319: ...er i s a p p l i e d t o t h e s t e p p i n g motor c o i l s a t t h a t t i m e t o execute t h e seek and s e t t l i n g o p e r a t i o n s s e c u r e l y with high t o r q u e A f t e r t h e...

Page 320: ...ck 00 s e n s o r o u t p u t a t TP3 TOS i n p u t o f LSI i s HIGH Track 00 s e n s o r d e t e c t s t h e l i g h t d i s t u r b i n g wing o f t h e head carriage t r a c k 00 p o s i t i o n S...

Page 321: ...r e a d i w r i t e LSI RDYO RDYO o u t p u t s i g n a l LOW FDD i s i n ready s t a t e DSEL DRIVE SELECT i n p u t s i g n a l LOW IDXO Negative INDEX p u l s e o u t p u t t o t h e h o s t c o n...

Page 322: ...E o r DRIVE STATUS s i g n a l u s i n g DCl IXZ o u t p u t t e r m i n a l s and DcS DCSW i n p u t t e r m i n a l s o f t h e LSI Refer t o t h e S p e c i f i c a t i o n and Schematic diagram as...

Page 323: ...i o n o u t p u t s i g n a l keeps LOW l e v e l while t h e SSI SIDE ONE SELECT However while t h e WG o r E G o u t p u t s i g n a l from t h e c o n t r o l LSI keeps HIGH l e v e l w r i t e or...

Page 324: ...c o n t r o l l e r The wpo o u t p u t goes t o L O W when t h e FPT s i g n a l from t h e f i l e p r o t e c t s e n s o r is LOW and when t h e DRIVE SELECT E i n p u t s i g n a l i s TRCX LOW...

Page 325: ...s h l e s s motor having 3 phase coils and bi polar d r i v e system The c o i l s are d r i v e n by t h e exclusive servo I C Energization and magnetized d i r e c t i o n of t h e c o i l s are c o...

Page 326: ...t e s t p o i n t s and v a r i a b l e resistors TP1 I n d e x TP2 E r a s e gate TP3 T r a c k 00 TP4 Pre amp R1 LPCB i s s u e J TP5 Pre amp TP6 D C OV TP7 D i f f e r e n t i a t o r TP8 D i f f...

Page 327: ...on the PCBA f r o n t OPT and the LED i s mounted on the DD motor Ass y s p i n d l e motor TP1 i s used f o r t h e following purposes a Confirmation of the disk r o t a t i o n a l speed b Rough co...

Page 328: ...h t h e erase head This TP i s used f o r the check of the required delay time of the erase gate s i g n a l a g a i n s t the WRITE GATE WG s i g n a l WRITE GATE input s i g n a l TP2 Erase g a t e...

Page 329: ...l e v e l change timing of the TRACK 00 s i g n a l i s not c o n s i s t e n t with t h a t of the TP3 s i g n a l 2 Sense timing of the track 00 position w i l l change i f you loosen the f i x i n...

Page 330: ...of the order of several hundred mVp p t o several Vp p which d i f f e r i n phase by 180 Both outputs a r e observed a t TP7 and TP8 respectively For an accurate observation of the waveforms use two...

Page 331: ...to use a small size c l i p to obtain a probe ground of the equipment 252...

Page 332: ...pulse Write and read 1F data and observe the pulse intervals at the READ DATA output line Then adjust the variable resistor so that the read data asymmetry takes the minimum value in Fig 220 Repeat ea...

Page 333: ...TEAC FD 55BR 521 DRAWINGS i PARTS LIST REV A...

Page 334: ...OWN AND PARTS L I S T 406 4 2 1 FDD 406 4 2 2 Screws and Washers 411 4 3 PCBA PARTS L I S T 412 4 3 1 PCBA ME D Control N P N 15532097 02 413 4 3 2 PCBA Front OPT N P N 15532091 00 414 4 4 PARTS LOCAT...

Page 335: ...iled break down Frame DD motor Ass y Spindle motor Stepping motor Ass y Set arm Ass y Collet Ass y Holder Ass y Lever shaft Ass y Clamp arm Ass y CSS sub ASS y Front bezel Ass y Front lever Ass y Head...

Page 336: ...Index sensor PCBA f i x i n g screws PCBA f r o n t OPT N Front bezel Ass y Front l e v e r CSS sub Ass y J5 PCBA f r o n t OPT C o l l e t Ass y J1 Signal i n t e r f a c e S e t arm Sub Ass y Fig 40...

Page 337: ...Spindle DD motor A s s y DD motor Ass y fixing screws Index sensor LED Lever shaft Head carriage Ass y Stepping motor Ass y 403...

Page 338: ...el screwsA fixing DD motor ASS Y A J 6 Stepping motor Head carriage Ass y Track 00 sensor 57 Spindle m t o r PCBA fixing screwsY L t e p p i n g motor fixing screws MFD control N Fig 403 External view...

Page 339: ...Name plate f LParts number of the FDD Fig 404 External view 0 4 405...

Page 340: ...4 2 MECHANICAL BREAK DOWN AND PARTS LIST 4 2 1 FDD Fig 405 Mechanical section break down 406...

Page 341: ...rts n a m e and ratings Q tY Description F r a m 1 Table 402 Parts l i s t of the FDD 29 15532097 02 30 15532091 00 31 17967267 68 32 17987261 68 407 PCBA WD control N 1 PCBA front OPT N 1 Front bezel...

Page 342: ...ts number i n Table 402 including small parts This is because that the head carriage and two guide shafts are supplied in a pair for the matched hole combination Two guide shafts are placed into the c...

Page 343: ...SPARE PAGE 409...

Page 344: ...Table 402 C Parts list of head carriage Ass y BR 410...

Page 345: ...8 s 9 s 11 E ring 4J l 1196080 00 ls SBoB1 00 16498081 01 16196618 00 18198082 00 16496818 01 S 13 Hy lar washer 0 11 4 1 8 For adjustment Wlar washer 0 2l 4 1 8 For adjustment Hylar masher 0 1 4 1 8...

Page 346: ...s following the PCBA version number The e a r l i e r the character i n the alphabets is the older the revision of the assembly 2 The newest assembly p a r t s have mark a f t e r the REV Parts with o...

Page 347: ...m 1 I 13193 2 I Photo interrupter c P 1 s I 1 CR 2 C R 3 cR4 cR5 I I 13411386 Dioda 1SSl3B 130403 7 Jumper wire JPI 01 130403 7 Jumper wire JH 01 13040377 Jumper wire JPI 01 r CRAl 1 13411398 Diode p...

Page 348: ...ms J II 11186183 Resistor RD 1 5U 18K o h s J 11982968 Resistor RN 1 41 2 W o h s F R 8 R 9 R 10 R 12 R 13 R 14 11186222 Resistor RD 1 51 2 B o h s J 11050121 Resistor RN 11 120 o h s J 119asO6s Resis...

Page 349: ...C10 c 1 1 c 12 C13 C 14 C 15 C 20 12907113 Capacitor CC 25V 0 022crF Z C 21 12907113 Capacitor CC 25V 0 022crF Z 12907098 Capacitor CC 5OV 470PF J 12907098 Capacitor CC 5OV 470PF J 12907648 Capacitor...

Page 350: ...apacitor CE 5OV 6 8uF V 12907113 Cawitor CC 25V 0 022uF Z 12907113 Cawitor CC 25V 0 022 uF Z 12907113 Capacitor CC 2SV 0 022uF Z L 1 L 2 L 3 Table 404 PCBA MFD control N parts list 4 5 413D ll 384 38...

Page 351: ...ngs Description Connector 6P Connector 5P I U1 11 384508 DO D1 13189406 ML RY 13189406 1U 11984508 Table 404 PCBA MFD control N parts list 5 5 Resistor 0 ohm 4 Post pins Unreplaceable 4 Post pins Resi...

Page 352: ...SPARE PAGE 413F...

Page 353: ...w52 Parts Nos Parts IUW and ratings Description 13419080 Phot transistor 13419060 Phot transistor 13040460 Jumper wire 5 lines 7 7 n 16787503 00 16787502 00 Index holder For w51 1 Sensor holder For w5...

Page 354: ...A version Refer t o VERSION TABLE I f the p a r t s w i t h an asterisk are not l i s t e d i n the corresponding column of the VERSION TABLE it means t h a t they are not used i n t h a t PCBA versio...

Page 355: ...VERSION REVISION 416...

Page 356: ...PCBA DD MOTOR SERVO PARTS LOCATION Type K R E V ISION 416B...

Page 357: ...PCBA DD MOTOR SERVO PARTS LOCATION Type G 416C...

Page 358: ...SPARE PAGE 416D...

Page 359: ...SPARE PAGE 416E...

Page 360: ...PCBA DD MOTOR SERVO SCHEMATIC Type S m 5v uc 5 12v W 1 2 0102 f I I 0 Pi15 r K l Pi12 4 71 U l O l M51784P ov 417...

Page 361: ...FCBA DD MOTOR SERVO SCHEMATIC Type K HSPO 5 0 4 Ill05 1 51 31...

Page 362: ...PCBA DD MOTOR SERVO SCHEMATIC Type G 12v ov RlM 2 2K 417C...

Page 363: ...SPARE PAGE 417D...

Page 364: ...SPARE PAGE 417E...

Page 365: ...PCBA HFD CONTROL N PARTS LOCATION e i i a _ _ e 11 44 L v e rsion 418...

Page 366: ...PCBA FRONT OPT N PARTS LOCATION R E V I SI ON V E R S I O N 0 E LED51 0 s W i P O 5 2 PCB ISSUE 419...

Page 367: ...SECTION 3 MAINTENANCE...

Page 368: ...isk since it may be effective to improve the reliability of data If some of the parts in the FDD are operated at a specially heavy duty or if the FDD is operated over 5 years it is recomended to repla...

Page 369: ...ral check and adjustment all over the FDD After the mechanical items of steps 1 4 electric performance items of steps 5 15 should be done 3 minutes 3 4 6 3 minutes 3 4 7 3 minutes 3 4 8 ktepsC h e c k...

Page 370: ...and applied FDD Notes 1 A l l SKAs are generally called a s SKA i n the following explana tion unless otherwise designated 2 SKAs in Table 3103 can be used also for a l l the conventional FD 55 series...

Page 371: ...or any of the following TEAC power unit can be used TEAC power unit PS 11 PS3 o r PS3 MINI b Minimum required current for SKA operation 12V 0 2A for SKA a for FDD 5V 1 2A for SKA for FDD c Required ac...

Page 372: ...t s e l f and i n s t a l l e d ROM a SKA3 hardware Issue E o r l a t e r b ROM i n s t a l l e d Version V1 06 o r l a t e r Note Issue and Version a r e shown on bottom p l a t e of the SKA3 2 Acces...

Page 373: ...ially available DC power supply or TEAC power unit PS3 or PS3 MINI can be used Note TEAC power unit PS I1 cannot be applied for the SKA3 as a rule because of small current capacity If it is temporaril...

Page 374: ...C When an SKA is not used 1 FDD controller and DC power supply user s system 2 Oscilloscope two channels 3 Frequency counter 4 Digital voltmeter 5 Thermometer and hygrometer 3107...

Page 375: ...all size 2 Special jigs a Max media jig for adjustment Jig C P N 17890746 00 b Max media jig for check Jig E P N 17890746 02 c Alignment adjustment jig P N 17851100 00 3 Disks a Work disk commercially...

Page 376: ...N 14900016 24 iii For High density double sided 96tpi FD SSGR P N 14900016 25 4 Other a r t i c l e s used during maintenance a Absolute alcohol Ethanol b Cottom swab o r gauze c Locking p a i n t Thr...

Page 377: ...gnated p o i n t s a f t e r t i g h t e n i n g o r a d j u s t i n g t h e s c r e w a I n s t a l l a t i o n screws of stepping motor M 3 2 p o i n t s b Adjustment s c r e w o f arm l i f t e r O...

Page 378: ...i n a t o r network o n l y f o r f u l l strap models d 54 Head connector e J5 PCBA f r o n t OPT c o n n e c t o r f 56 S t e p p i n g motor connector g J 7 S p i n d l e motor DD motor Ass y c o n...

Page 379: ...F i l e protect sensor PCBA front OPT Index sensor Top view Fig 3201 Types of connectors 3203...

Page 380: ...wn in Fig 3202 carefully push up the edges of the upper protruding area of the connector little by little with the finger nails or with a screwdriver Upper protruding area Housing clamper Post pin sid...

Page 381: ...s h o r contamination adheres on t h e contact area of t h e p i n or t h e PCB s i d e post pin I f t h e r e is remove it Contact f a i l u r e may happen i f any of these t h r e e p o i n t s i s...

Page 382: ...t h e cable with a p a i r of tweezers i n t h e d i r e c t i o n indicated by t h e arrow mark Refer t o Fig 3204 7 Projection Stopper p u l l up c l a m p securely Cable Contact area Lm Fig 3204 S...

Page 383: ...PCBA MFD control iii Guiding t h e cable with a t i p o f your l e f t f i n g e r and push t h e cable i n t o t h e receptacle securely i v Confirm v i s u a l l y t h a t t h e cores are not bent n...

Page 384: ...tweezers and fit the core wires in line against the 57 receptacle iii Push the cable into the receptacle securdjy not to be bended nor folded iv Depress the center area of the flat cable against the...

Page 385: ...t bridge of t h e set arm 2 Hold t h e head cable between t h e head connector and the frame so t h a t the cable has appropriate space margin a g a i n s t t h e mechanical p a r t s when the head c...

Page 386: ...o n t o i d e n t i f i c a t i o n mark V of t h e connector so t h a t it l o c a t e s a t p i n 1 s i d e 5 Connect t h e FD P W R OUTPUT o f t h e SKA and 52 of t h e FDD with t h e power l i n...

Page 387: ...C 1 2 V VOLTAGE 14 Adjust t h e ELI pcwtr voltage so t h a t t h e D A T A i n d i c a t o r XX XX V i n d i c a t e s a value within t h e range of 12 00 2 0 24V 15 Key i n F STOP Note The above item...

Page 388: ...DC power supplies 12v Sv A PCBA M F D c o n t r o l LConnect t h e g r e e n w i r e t o TP8 s i d e F i g 3206 Connection o f c o n v e n t i o n a l SKA 3212...

Page 389: ...h e c a r t r i d g e is fixed t o W s i d e Cartridge type m EF G r k FD 55V A J S l i d e switch 262422 ZOW 10161412100 6 4 ID1 2 Fig 3207 Cartridge s e t t i n g f o r FD 55BR and F R 3 S e t t h e...

Page 390: ...of the c a r t r i d g e parameter a r e read i n t o the SKA3 Note Be sure t o push the RESET switch when a c a r t r i d g e i s changed o r a s l i d e switch i s r e s e t 12 S e t the F D PWR swi...

Page 391: ...e i t e m s 1 41 9 111 13 17 may be o m i t t e d f o r replacement o r temporary power o f f o f t h e FDD I n t h i s case remain t h e DC p o w e r on f o r t h e SKA3 and c o n t r o l t h e FDD p...

Page 392: ...I w N P m I Check cable 2 I FDD 1 1 SKA FDD interface cable 12V1 5V Power a Cartridge cable I t I TGreen cable Pin 1 I 1 FD INTERFACE Fig 3200 Connection of SKA3...

Page 393: ...o maintain t h e main DC power on f o r t h e successive operations The i n i t i a l s e t t i n g of t h e following i s not required i f t h e maximum t r a c k number i s t h e same as tfie i n i...

Page 394: ...A i s depressed The i n i t i a l setting of the following is not required i f the step rate and the settling time are the same a s the i n i t i a l values of the SKA The following shows the 1 Key i...

Page 395: ...operation 7 Depress F key STOP Completion of settling time setting e g 48tpi 6msec seek model Step rate 6msec Settling time 15msec DB 60 F 150 F 48tpi 4msec seek model Step rate 4msec Settling time l...

Page 396: ...ot used i e when it is substituted with a commercially available disk and no accurate measurement is required A Conventional SKA 1 Innermost track read level a Key in DO CALIBRATION READ LEVEL b Calib...

Page 397: ...ee digits of the DATA 0 indicator XXXX c Key in a new calibration value of side 0 written on the level disk label three digits Max d Key in F Completion of side 0 calibration setting e Side 1 calibrat...

Page 398: ...esolution a Key in D1 CALIBRATION RESOLUTION b The same as in i t e m 1 b 9 e g D o u b l e sided FDD S I D E 0 READ LEVEL 103 S I D E 1 REA2 LEVEL 95 S I D E 0 RESOLUTION 96 SIDE 1 RESOLUTION 98 DO 1...

Page 399: ...A the initial setting of the following is not required A Conventional SKA 1 SIDE 0 alignment a Key in EO CALIBRATION SIDE 0 ALIGNMENT b Calibration value set at that time is indicated in the latter tw...

Page 400: ...ndicated the polarity is positive c Key in a polarity and a new calibration value three digits Max of side 0 written on the alignment disk label Refer to item l c as to the polarity designation Notes...

Page 401: ...the p o l a r i t y i s minus when a value i s negative Fig 3209 Calibration of alignment lobe pattern INDEX output signal 1 7 I Index burst TP4 S F t Index burst timing Notes 1 The index timing is c...

Page 402: ...y Depress B key only f o r minus designation No designation i s required f o r p l u s d Depress F key Completion of s i d e 0 c a l i b r a t i o n s e t t i n g e Side 1 c a l i b r a t i o n value...

Page 403: ...Depress F key Completionof side 0 calibration setting e Side 1 calibration value set at that time is indicated in the latter three digits of the DATA 1 indicator XXXX u s and the polarity is indicated...

Page 404: ...t from 50 a t 9 6 t p i FDD The i n i t i a l s e t t i n g of t h e following i s n o t required i f t h e r e l a t i v e humidity i s t h e same as t h e i n i t i a l value 50 of t h e SKA 1 Key i...

Page 405: ...d not feel concern about this setting for the S 3 1 Track alignment of 96tpi FD 55FR GR Key in DD to confirm that the H GAIN indicator is on 2 Track alignment of 48tpi FD SSBR and other items Confirm...

Page 406: ...were unless otherwise designated For a model with head load solenoid set the HS strap to on state and the HL strap should be o f f Notes 1 I f the strap position of the FDD is changed from the initia...

Page 407: ...l o f i n t e r f a c e connector p i n No 34 READY OPEN o r o t h e r optional s i g n a l s is TRUE L O W l e v e l RDY i n d i c a t o r o f t h e SKA turns on Refer t o t h e Specification as t o...

Page 408: ...ator s h a l l be returned t o the i n i t i a l condition a f t e r completion of t h e maintenance For t h e fixed type terminator without I C socket soldered on PCB above i n s t r u c t i o n is n...

Page 409: ...through t h e check cable and F D D i n t e r f a c e cable A l s o these s i g n a l s can be observed by an oscilloscope using t h e test p o i n t s on an SI A 4 Head load of CSS model For a CSS m...

Page 410: ...oom temperature and humidity The magnetic head disk s t e e l b e l t etc might s u f f e r from dust and d i r t i f t h e maintenance i s not undertaken i n a clean environment 7 Disk There a r e tw...

Page 411: ...and start t h e spindle motor Notes 1 Do not use a damaged cleaning disk 2 Be sure t o use a double sided cleaning disk Side 0 lower s i d e and s i d e 1 upper s i d e heads w i l l be cleaned a t t...

Page 412: ...e l e c t by key 0 DSO i n d i c a t o r t u r n s o n 3 Key i n CO and confirm t h a t t h e TRACK i n d i c a t o r of t h e SKA becomes 00 RECALIBRATE 4 I n s t a l l an appropriate cleaning disk S...

Page 413: ...t t i n g o u t o f place 2 Close t h e set arm by turning the f r o n t l e v e r 3 In t h i s condition i t e m 2 a d j u s t t h e set arm so t h a t t h e v i s i a l gap between the collet s h a...

Page 414: ...fCollet shaft retam 2 Set arm fixing screws between c o l l e t s h a f t and set arm hole Front l e v e r Fig 3401 Adjustment of s e t arm position 3402...

Page 415: ...e MAX media j i g E over t o i n s e r t it f o r pass s i d e and closing the f r o n t l e v e r confirm t h a t the l e v e r can be closed 4 I f the i t e m 2 o r 3 i s not s a t i s f i e d a d j...

Page 416: ...d torque e Confirm i t e m s 1 through 3 f Check f o r t h e f i l e p r o t e c t sensor according t o i t e m 3 4 5 g Check and a d j u s t t h e index b u r s t timing according t o item 3 4 15 L P...

Page 417: ...lder 7 E Holder f i x i n g screws 2 each s i d e Fig 3403 Adjustment of holder p o s i t i o n 1 7 Front bezel Front l e v e r MAX Wing media j i g Fig 3404 Adjustment of holder p o s i t i o n 2 340...

Page 418: ...F D c o n t r o l Triggering should be done by t h e head load command Oscilloscope range The 1st channel DC mode 2V 20msec The 2nd channel AC mode 0 5 T l V 20msec Note For t h e purpose of check an...

Page 419: ...y Note Viewed from f r o n t bezel side Fig 3405 Gap of arm l i f t e r Arm l i f t i n g p a r t Arm l i f t e r adjusting screw lifter Locking p a i n t LHead load solenoid Ass y Head carriage Ass y...

Page 420: ...e unload command a s shown by dotted l i n e i n Fig 3407 Note This i t e m s h a l l be executed when the s i d e 1 head is selected I f the s i d e 1 head i s l i f t e d too high during unload oper...

Page 421: ...the s p e c i f i e d range a d j u s t according t o the following procedure a Execute items 3 through 10 b Loosen the unload adjusting screw u n t i l t h e unload l e v e l is observed a t l O O m...

Page 422: ...wly In the process of drawing out the side 0 and side 1 heads s h a l l not catch the head window edge of the disk jacket opening area of the jacket t o make the head be i n contact with the disk surf...

Page 423: ...d adjustment i n t h i s i t e m it i s required t o set t h e s t r a p s according t o i t e m 3 2 4 8 1 4 Key i n BC F DRIVE SELECT observation 5 S t a r t t h e spindle motor by key 5 MON i n d i...

Page 424: ...l l be executed when t h e s i d e 1 head i s selected SIDE 1 i n d i c a t o r t u r n s o n I f t h e s i d e 1 head i s l i f t e d too high during unload operation tapping sound increases and d i...

Page 425: ...ears a t lOOmsec a f t e r the unload command d Key i n F STOP e Key i n C1 SEEK TMAX and execute items 10 and 11 f Confirm unload level according to item 12 If the unload level is observed a t lOOmse...

Page 426: ...n s e r t t h e d i s k slowly and confirm that t h e d i s k jacket does not touch t h e s i d e 0 nor s i d e 1 head and goes i n t o t h e FDD smoothly with appropriate space margin 2 2 I f t h e...

Page 427: ...g a i n s t t h e s i d e 0 head See Fig 3409 Tide head r L S i d e 0 head Fig 3409 Gap between s i d e 0 and s i d e 1 heads 3 After opening t h e f r o n t l e v e r i n s e r t a work d i s k slow...

Page 428: ...h e disk a Disk is not f u l l y inserted Rotates about 90 b Disk is f u l l y inserted and f r o n t lever is close Fig 3410 Cam r o t a t i o n of CSS Ass y 6 I n s e r t a work disk and start the s...

Page 429: ...of t h e jacket t o make the head be i n contact with t h e disk surface and t h a t the jacket can be drawn out smoothly with appropriate space margin 5 Confirm t h a t the cam natural color of the C...

Page 430: ...11 Key i n Cl SEEK T W 12 Confirm as i n item 10 3418...

Page 431: ...a j i g C from open s i d e and set it so t h a t t h e notch A area i s located on t h e l i g h t pass from t h e f i l e p r o t e c t sensor LED See Fig 3411 4 Adjust t h e o r i e n t a t i o n o...

Page 432: ...LED indicator Y Fig 3411 Check of f i l e protect sensor File protect sensor 3420...

Page 433: ...e l i g h t path from the f i l e p r o t e c t sensor LED See Fig 3411 3 Adjust the orientation of t h e F D D so t h a t it is not exposed with strong l i g h t 4 Confirm that the WPROT indicator o...

Page 434: ...re General method 1 Connect a frequency counter t o 1 Index on the PCBA MFD control or t o t h e INDEX interface signal l i n e 2 I n s t a l l a work disk and start the spindle motor 3 Set t h e head...

Page 435: ...r n s o n 4 Execute d r i v e select by key 0 DSO i n d i c a t o r t u r n s o n 51 Key i n lCO and confirm t h a t t h e TRACK i n d i c a t o r becomes 00 RECALIBRATE 6 Key i n C3 INDEX INTERVAL 7...

Page 436: ...he WRITE GATE interface l i n e and the other channel t o TP2 Erase gate delay on the PCBA MFD control Oscilloscope range For both channels DC mode 5V 100psec 2 I n s t a l l a work disk and s t a r t...

Page 437: ...l l o w i n g range E r a s e o f d delay FD sSBR GR 8 30 3 9 0 p s e c FD 55GR 5 3 0 5 9 0 u s e c WRITE GATE 7 E r a s e on delay TP2 E r a s e g a t e F i g 3 4 1 2 E r a s e on delay WRITE GATE TP...

Page 438: ...ect by key 0 DSO i n d i c a t o r t u r n s o n 5 Key i n 7 WRITE GATE ON 6 Confirm t h a t t h e DATA DATA 0 f o r SKA3 i n d i c a t o r XXXX PSI shows a value within t h e following range E r a s...

Page 439: ...e innennost track 4 Execute the head loading 5 Repeat the cycle of one w r i t e rotation and one read rotation Write data should be the fixed pattern of 2F 250KHz of W R I T E DATA frequency f o r F...

Page 440: ...CSS Ass y in item 3 4 4 CSS model without head load solenoid the flexture on which the head piece is located may be deformed Remove the disk Then open and close the front lever slowly t o observe the...

Page 441: ...ched under the s e t arm does not touch the jacket surface replace the pads Refer t o Fig 405 in Parts L i s t Caution I f the jacket surface i s excessively pressed by the pads the spindle motor migh...

Page 442: ...XXXX mV i n d i c a t e s t h e average read l e v e l a t TP4 and TP5 Pre amp a f t e r each cycle of operation one r o t a t i o n of w r i t e and one r o t a t i o n o f read is finished a When S...

Page 443: ...h a t s i d e 0 and s i d e 1 read l e v e l s measured i n i t e m 8 are more than 80 o f that i n i t e m 9 11 Key i n CO RECALIBRATE and execute i t e m s 7 through 10 i n t h e similar way 12 Pos...

Page 444: ...nge DC mode 2V 0 5 lpsec 2 I n s t a l l a work disk and s t a r t the spindle motor 3 Set the head t o the innermost track 4 Execute the head loading 5 Execute 1F write operation for one rotation of...

Page 445: ...Rl on t h e PCBA MFD control so t h a t the asymmetry takes a small value while repeating 1F w r i t e and 1F read operations alternately b Repeat the operation i n i t e m a f o r side 0 and side 1 h...

Page 446: ...c t a k e it apart from t h e FDD Then measure t h e asymmetry and a d j u s t again b I n f e r i o r d i s k Replace t h e work d i s k with a new one c I n f e r i o r head Replace t h e head c a r...

Page 447: ...ode 2V 0 1 O 2psec 4 I n s t a l l a work d i s k 5 S t a r t t h e s p i n d l e motor by key 5 MON i n d i c a t o r t u r n s o n 6 Execute d r i v e select by key 0 DSO i n d i c a t o r t u r n s...

Page 448: ...or a model with a variable resistor for asymmetry adjustment a Adjust the variable resistor R l on the PCBA MFD control so t h a t the asymmetry takes a small value by keying i n D4 b Execute the oper...

Page 449: ...erations a r e repeated Asynmetry values of s i d e 0 and side 1 heads a r e indicated on the D A T A 0 and D A T A 1 indicators XXXX ns successively a f t e r each cycle of operation D A T A 0 indica...

Page 450: ...asymmetry changes at every measurement rough adjustment will be done b The variable resistor shall be so adjusted that both asymmetry for side 0 and side 1 heads take the minimum value Refer to Fig 22...

Page 451: ...annels 2 I n s t a l l a l e v e l disk and s t a r t the spindle motor 3 Set the head t o the innermost track 4 Execute the head loading 5 Execute 2F write operation f o r one r o t a t i o n of the...

Page 452: ...respectively 10 I f the value i n item 8 or 9 is out of the specified range following causes are assumed a Inferior disk Disk and or jacket i s deformed o r damaged Replace the level disk with a new o...

Page 453: ...Replace the PCBA MFD control according t o item 3 5 7 11 Eject the l e v e l disk and release the Invert and Add modes of the oscilloscope 3441...

Page 454: ...alibration value of the l e v e l d i s k should be set previously i n t h e SKA 8 The D A T A indicator XXXX mVo p i n d i c a t e s t h e average read level a t TP7 and TP8 Dif amp a When SKA3 is us...

Page 455: ...Innermost track read level FD 5SBFtJGR 4OOmVp p Min FD SSFR 3OOmVo p Min 10 If the value in item 9 is out of the specified range refer to item 10 of General method 11 Eject the level disk 3443...

Page 456: ...Set e i t h e r of t h e channels t o Invert mode and Add both channels 2 I n s t a l l a level disk and s t a r t the spindle motor 3 Set t h e head t o the innermost track 4 Execute the head loadin...

Page 457: ...the following range Innermost track resolution 60 Min 11 Execute items 5 through 10 f o r s i d e 0 and s i d e 1 heads respectively 12 I f the value i n i t e m 10 or 11 is o u t of the specified ran...

Page 458: ...ace the head carriage Ass y according to item 3 5 1 e Inferior PCBA MFD control Replace the PCBA MFD control according to item 3 5 7 13 Eject the level disk and release the Invert and A d d modes of t...

Page 459: ...ation value of t h e l e v e l d i s k should be set previously i n t h e SKA 8 The D A T A indicator X X X X I i n d i c a t e s t h e resolution a t TP4 and TP5 Pre amp 1 a When SKA3 is used By keyi...

Page 460: ...Innermost track resolution 609 Min 10 If the value i n i t e m 9 i s out of the specified range refer t o i t e m 12 of General method 11 Eject the level disk 3448...

Page 461: ...en if the environmental condition is within the specified operational condition extreemly high or low temperature or high or low humidity should be avoided Check and adjustment should be done after tw...

Page 462: ...nd from the host side There w i l l be no damage to the FDD i t s e l f b I n s t a l l and eject an alignment disk during p o w e r on of the FDD c Before i n s t a l l a t i o n be sure t o check t...

Page 463: ...t e i t h e r of t h e channels t o I n v e r t mode and Add both channels 2 I n s t a l l an alignment d i s k and s t a r t t h e spindle motor 3 Execute the head loading 4 S e t the head t o the f...

Page 464: ...E For a 48tpi FDD the lobe pattern in Fig 3418 shall be observed at the even track while it shall be observed at the track of multiple number of four for a 96tpi FDD 61 After one or several step outs...

Page 465: ...items 4 through 10 for side 0 and side 1 heads respectively 122 If the value in item 10 or 11 is out of the specified range adjust the track alignment according to the following procedure a Loosen the...

Page 466: ...e following value Calibration value Relative humidity 50 K 100 e g 96tpi Calibration value 6 Relative humidity 35 6 35 50 x 0 42 12 3 0 6 35 50 x 0 42 o 88 100 Therefore the t a r g e t value of VB wh...

Page 467: ...ack 00 sensor according to i t e m 3 4 13 i Check the track 00 stopper according to i t e m 3 4 14 131 Release the Invert and Add modes of the oscilloscope Alignment adjustment j i g Fig 3419 Adjustme...

Page 468: ...6 t p i F D D FD SSFR GR using a convent ional SKA Refer t o i t e m 3 2 4 7 Key i n DD H GAIN i n d i c a t o r t u r n s On 5 I n s t a l l an alignment disk 6 S t a r t t h e spindle motor by key...

Page 469: ...ic phase A o f t h e stepping motor For a 48tpi FDD t h e lobe p a t t e r n s h a l l be observed a t t h e even track while it s h a l l be observed a t t h e t r a c k o f multiple number of four f...

Page 470: ...the stepping motor a l i t t l e b I n s e r t the alignment adjustment j i g o r M 3 screw from the back side of the F D D as shown i n Fig 3419 c Key i n E3 and adjust the j i g o r M3 screw so that...

Page 471: ...and adjust the track 00 sensor according t o item 3 4 13 i Check the track 00 stopper according to i t e m 3 4 14 16 Release the Invert and Add d e s of the oscilloscope 17 When the H GAIN indicator o...

Page 472: ...h as possible 1 Connect an oscilloscope o r d i g i t a l voltmeter t o TP3 Track 00 sensor on t h e PCBA ME D control Oscilloscope range DC mode 1V 2 I n s t a l l a work disk and start t h e spindle...

Page 473: ...i o n amp of the PCBA M F D control Oscilloscope range AC mode 0 2 0 5V 20msec b I n s t a l l an alignment disk The t r a c k alignment should be previously adjusted according t o i t e m 3 4 12 cl M...

Page 474: ...owing range TP3 voltage a t t r a c k 01 4 8 t p i o r t r a c k 02 96tpi 1 V 3V 2V approx c e n t e r i Confirm the items 4 through 7 j Adjust t h e t r a c k 00 sensor p o s i t i o n so t h a t t h...

Page 475: ...Head carriage Ass rack 00 sensor PCBA fixing screws Fig 3420 Adjustment of track 00 sensor Y 3463...

Page 476: ...k RA1 f o r terminator on the PCBA M F D control t r i g g e r 3 Key i n B8 F STEP observation 4 I n s t a l l a work disk and s t a r t the spindle motor by key 5 MON indicator turns on 5 Execute dri...

Page 477: ...1 2 3 4 5 TP3 Track 00 sensor t A 48tpi FD 55BR Track 00 d e t e c t i o n 4 SKA DOUT 1 2 3 4 5 1 2 3 4 5 TP3 2v Track 00 sensor 1 ov __I Track 00 detection 9 6 t p i FD55FR GR Fig 3421 Track 00 sens...

Page 478: ...alignment should be previously adjusted according t o i t e m 3 4 12 c Key i n CO and confirm t h a t t h e track indicator becomes 00 RECALIBRATE d Key i n the following number and confirm t h a t t...

Page 479: ...BA p o s i t i o n so that t h e t r a c k 00 d e t e c t i o n t i m i n g falls w i t h i n t h e s p e c i f i e d range k Repeat t h e adjustment so t h a t t h e t i m i n g satisfies t h e s p e...

Page 480: ...i m e l5msec FD 55BR 4msec seek model Step r a t e Imsec S e t t l i n g t i m e lOmsec FD sSFR GR Step r a t e 3msec S e t t l i n g t i m e 15msec 61 Key i n CO and confirm t h a t t h e TRACK i n d...

Page 481: ...es t o inner track and then it returns t o the track 00 position auto recalibration Confirm t h a t the head carriage 11 If t h e value i n i t e m 8 o r 10 i s out of the specified range a d j u s t...

Page 482: ...k 00 and t r a c k XX Confirm t h a t no impact sound can be heard between t h e head c a r r i a g e and t h e o t h e r f i x i n g p a r t s t r a c k 00 s t o p p e r 5 Turn o f f t h e FDD p o w...

Page 483: ...ead carriage A s s y tepping motor Track 00 sensor Depress head carriage toward the rear end Fig 3422 Check of track 00 stopper 3471...

Page 484: ...sec S e t t l i n g t i m e 15msec 5 Key i n 9 STEP OUT 6 Confirm t h a t t h e head c a r r i a g e does n o t move even i f 9 is keyed i n head carriage rests on t r a c k 00 7 Key i n CO and key i...

Page 485: ...i t i v e t r i g g e r by TP1 Oscilloscope range The 1st channel I X mode 2V SOusec The 2nd channel AC mode 0 5V SOpsec 2 I n s t a l l an alignment disk and s t a r t t h e spindle motor 3 Execute...

Page 486: ...a d j u s t the index sensor position according t o the following procedure a Loosen the two fixing screws see Fig 3424 of the PCBA front OPT and adjust its position t o make the t r u e value of t h...

Page 487: ...CBA front OPT justing direction PCBA front OPT Index sensor Fig 3424 Adjustment o f index sensor 3475...

Page 488: ...h e head t o t h e index check t r a c k by t h e following operation 4 8 t p i FD 55BR Key i n C2 01 and confirm t h a t t h e TRACK indication becomes 01 96tpi FD SSFRJGR Key i n C2 02 and confirm...

Page 489: ...ts position so that the DATA indication under execution of item 7 shows the median value i n the specified range of i t e m 8 b Repeat the adjustment so that the DATA indication takes the median value...

Page 490: ...S8 3 Apply alcohol to locking paint areas on the head carriage There are four points of shaded area as shown in Fig 3501 and Fig 3502 4 Wait a minute 5 Turn the FDD over so that the spindle motor bott...

Page 491: ...h e carriage 7 Make t h e belt spring s l i d e i n the reverse direction of the a r r o w mark i n Fig 3501 using a p a i r of tweezers and make the locking paint 2 and 3 free carriage Then remove t...

Page 492: ...i o r points f o r these belt and spring they may be used a f t e r cleaning the surface carefully with alcohol and gauze 2 Pay a t t e n t i o n not t o darnage the surface of t h e steel belt or th...

Page 493: ...he b e l t i s tensioned straightly Pay attention not t o damage the surface of the b e l t or the capstan Note Do not pinch the upper arm of the head carriage when move it manually Pinch the rear sid...

Page 494: ...heck t h e CSS Ass y according t o i t e m 3 4 4 23 Make t h e head move continuously between t h e t r a c k 00 and the innermost t r a c k and confirm t h a t t h e s t e e l b e l t does not meande...

Page 495: ...e read level accoding to item 3 4 10 31 Check the resolution according to item 3 4 11 32 It is recommended to connect the FDD to the system for overall test Refer to item 3 2 5 1 for the window margin...

Page 496: ...3 through 8 4 Remove t w o fixing screws Fig 405 S9 of the stepping motor Ass y Fig 405 No 27 and remove the stepping motor with the s t e e l belt 5 Remove a screw Fig 405 S1 on the capstan of the st...

Page 497: ...t runs on t h e center of t h e b e l t spring when viewed from t h e bottom side Refer t o Fig 3501 11 After moving t h e head carriage several times manually tighten t h e f i x i n g screw of t h e...

Page 498: ...te I f the s t e e l b e l t is replaced execute t h e continuous seek operation i n i t e m 12 f o r 3 minuites approx 13 Adjust the t r a c k alignment according t o i t e m 3 4 12 14 Adjust the t r...

Page 499: ...he r o t o r side PCBA side 3 I n s t a l l a new DD motor Ass y i n the reverse order of i t e m s 1 and 2 Refer to i t e m 3 2 2 5 a s t o t h e handling of 57 connector Note The spindle area of the...

Page 500: ...Adjust the track alignment according t o item 3 4 12 8 Check o r adjust the track 00 sensor position according t o i t e m 3 4 13 9 Check or adjust the index burst timing according to i t e m 3 4 15 3...

Page 501: ...E ring Fig 405 512 which f i x e s t h e c o l l e t Ass y Fig 405 No 9 t o the set arm and remove the c o l l e t and the pressure spring Fig 405 No 10 3 I n s t a l l a new c o l l e t Ass y i n the...

Page 502: ...e r r i n g i t e m B Replacement procedure 1 Disconnect t h e head load solenoid connector J8 21 Remove two f i x i n g screws Fig 405 S2 t o r e m v e t h e head load solenoid Ass y Fig 405 No 20 3...

Page 503: ...set m Lea Ass armJ d Y load Fig 3504 Installation of the head load solenoid Ass y solenoid 3514...

Page 504: ...ocedure 1 Remove a fixing screw Fig 405 S2 t o remove the CSS Ass y Fig 405 No 21 from the frame 2 I n s t a l l a new CSS Ass y i n the reverse order Be careful t o i n s t a l l the arm l i f t e r...

Page 505: ...ee fixing s c r e w s Fig 405 S 3 3 I n s t a l l a new P C B A i n the reverse order 4 Set the straps and terminator a s they were on the old PCBA 5 Check the f i l e protect sensor according t o i t...

Page 506: ...12 I t is recommended to connect the FDD to the system for overall test Refer to i t e m s 3 2 5 1 f o r the window margin test 3517...

Page 507: ...dure 1 Disconnect PCBA f r o n t OPT connector J5 2 Remove two f i x i n g screws Fig 405 S7 t o remove t h e PCBA f r o n t OPT Fig 405 No 30 3 I n s t a l l a new PCBA i n the reverse order 4 Check...

Page 508: ...e f r o n t bezel Ass y Fig 405 No 31 and draw t h e f r o n t bezel o u t 3 I n s t a l l a new f r o n t bezel Ass y i n t h e reverse order For t h e i n s t a l l a t i o n o f t h e f r o n t bez...

Page 509: ...pment f o r each referring i t e m B Replacement procedure 1 Draw out the f r o n t lever Ass y Fig 405 No 32 2 I n s e r t a new f r o n t lever Ass y f u l l y against the lever shaft a s it was 3 C...

Page 510: ...N S P E C STO LED51 RED I 15532091 00 15532091 01 STD LEDSl GREEN1 LEDSl GREEN1 STD 1553209 1 07 STO LED51 AMflERl 15532091 10 VERSION TABLE NOTES ABBREVIATED NAMES ARE AS FOLLOWS RED GREEN M E R FRON...

Page 511: ...A S E A im qS T E P P I N G P H A S E M A MOTOR I PHASE NE A S S Y I COY A I DOOR CLOSE I ASS Y Q4 I J 2 S l G N A L S W I T H OOUELE A S T E R I S K S ARE USEO O N L Y FOR O P T I O N A L VERSIONS R...

Page 512: ...Y 0 7 I E 513 I H L H A L F STRAP 08 7 7 z f 0 4 I E1 523 C S S F U L L STRAP CUSTOM 1 1 1 0 1 2 00 0 1 I L A S S Y I L ASS Y I L SOL A S S Y 1 5 1 6 03 5 7 6 ICSS FULL STRAP I E T C D R I V E S T A T...

Page 513: ...L O V E R S I O N M A I N S P E C P A R T S f 1 CONlROL S I G N A L S T Y P I C A L 10 V E R S I O N M A I N S P E C P A R T S 0 CONTROL rn FRON 532091 XX PT 532092 XX S I G N A L S P N 1930727X XX VE...

Page 514: ...EP O I I C T I O I SELECT YOTW 01 teseeveo mivc SELECT I mivc PLLCT o I I W X 1 S E W E O Ill USL HtAO LOA0 UCSEMO S I m L am c m Imr tlZV W W t5v FASlCU 11 14 12 10 8 s a a m m m a b s J1 2 I2 4 6 I...

Page 515: ...ANCE SVYBOLS FOR R RA C AM0 L ARE F i l S 0 i 2 l J IS I ilO Y t Z O 1 V ti O lOS Z tlO 2OS 4 INOUCTOR L1 VALUES ARE I N YlCRO HEYRIES i5S J UNLESS OTHERVISE SPECIFIED 3 CAPACITOR C1 VALUES ARE I N MI...

Page 516: ...y represented by l i s t e d parts number i n Table 406 includes these guide shafts which parts number i s different from t h a t of a head carriage Ass y i t s e l f without these guide shafts Refer...

Page 517: ...first should have priority 5 The required time for replacement includes the time for basic check and adjustment after the replacement 6 Use the designated parts number for ordering the spare parts 424...

Page 518: ...Table 406 FD 55BR recommendable spare parts list Spare parts Parts name Description Parts No Head carrirce Ass y BR Note 1 17967603 00 Steppinc motor A s y...

Page 519: ...Software...

Page 520: ...Software...

Page 521: ...Printer 24 SystemClock 26 Sound Multiplexer 30 Diskette I O Support for Diskette Only 31 Equipment 38 Memory Size 39 Bootstrap Loader 39 MachineIdentification 40 EEPROM 41 BIOS Sound Support 43 Keybo...

Page 522: ...ovided with a software interrupt which transfers execution to the routine Entry parameters to BIOS routines are normally passed in CPU registers Similarly exit parameters are generally returned from t...

Page 523: ...s Followingis a quick reference list of software interrupts for all device I O and system status services Service Video Display Equipment Memory Size Diskette Serial Communications SystemServices Keyb...

Page 524: ...in AH 10H Extended keyboard read AH 11H Extended ASCII status AH 12H Extended shift status read keyboard buffer Function Descriptions Read Keyboard Read the nextcharactertyped atthe keyboard Return t...

Page 525: ...ions z no character available NZ AL AH keyboard scan code a character is available in which case ASCII value o f character Get Shift Status Return the current shift status Entry Conditions AH 2 Exit C...

Page 526: ...Buffer full C Operation failed Extended Keyboard Read Entry Conditions AH 10H Exit Conditions AL AH keyboard scan code ASCII value of Character Extended ASCII Status Entry Conditions AH 11H Exit Condi...

Page 527: ...pressed Bit 2 CTRL pressed Bit 1 Bit 0 CAPS LOCK active NUM LOCK active SCROLL LOCK active LEFT SHIFT pressed RIGHT SHIFT pressed reset false SYS REQ pressed CAPS LOCK active NUM LOCK active SCROLL LO...

Page 528: ...lls INT 10H AH 00 AH 01 AH 02 AH 03 AH 05 AH 06 AH 07 AH 08 AH 09 AH O A AH OB AH OC AH OD AH O E AH OF Set Video Mode Set Cursor T y p e Set Cursor Position Read Cursor Position Select Active Display...

Page 529: ...3 Color Palette Interface Set Individual Register Set Border Color Set All Palette Registers and Border Write String Write CharacterString Write CharacterStringand Move Cursor Write Characterand Attri...

Page 530: ...raphics Modes AL 4 AL 5 AL 6 AL 7 320x200 color graphics 320x200 black and white graphicswith 4 shades 640x200 black and white graphics with 2 shades monochrometext Additional Modes AL 8 160x200color...

Page 531: ...blinking cursor Bits 5 6 0 produces a visible blinking cursor Bits 4 0 start linefor cursor within charactercell CL bit values Bits 4 0 end linefor cursorwithin charactercell Set Cursor Position Write...

Page 532: ...sor Type AH 1 CX Select Active Page Select active displaypage valid in alpha mode only Entry Conditions AH 5 AL AL AL AL AL AL 0 through 7 0 through 3 80H read CRT CPU page registers 81H set CPU page...

Page 533: ...of scroll window CL column of upper left comer of scroll window DH row oflowerright corner of scroll window DL column of lowertight cornerof scroll window BH attribute alpha modes orcolor graphics mo...

Page 534: ...column of lower right cornerof scroll window BH attribute alpha modes of color graphicsmodes to be used on blank line See ScrollUp AH 6 for at tributevalues and Set Color Palette AH 11 for color valu...

Page 535: ...racter for alpha modes or color of character for graphics modes If Bit 7 of BL is set the color of the character is XOR ed with the color value See Scroll Up AH 6 for attribute values and Set Color Pa...

Page 536: ...ack and white modes BL 0 1for white BL 1 lforblack In 4 color graphics modes BL BL In 16color graphics modes 1 Set default palette to the number 0 or 1 in BL 0 1 1 green 2 red 3 yellow 1 cyan 2 magent...

Page 537: ...umnnumber AL color value When Bit 7 of AL is set the resultant color value of the dot is the exclusiveOR of the current dot color value and the value in AL Read Dot Read a pixel dot Entry Conditions A...

Page 538: ...Entry Conditions AH OEH AL characterto write BL BH dispZaypage alpha modes foreground color graphics mode Get CRT Mode Get the current video mode Entry Conditions AH OFH Exit Conditions AL current vi...

Page 539: ...register BL BH color value to store numberof palette register 0 15 to set AL 1 Set border color register BH color value to store AL 2 Set palette color value to store and border registers ES DX points...

Page 540: ...of string attributes do not count startingcursorposition DH row DL column page number for text modes attributefor characters graphics modes 00 Characters only string cursor not updated 01 Characters o...

Page 541: ...C serial communications port This device is labeled the auxiliary AUX I O device in the device list maintained by MS DOS Software Interrupts 14hex 20 dec Function Summary AH 0 Reset Commport AH 1 Tran...

Page 542: ...1 0 Parity Stop Bits WordLength Entry Conditions AH 0 AL RS 232Cparameters as follows DX port number 0 or 1 b I I 000 110baud 00 none 0 1bit 10 7bits 001 150baud 01 odd 1 2 bits 1 1 8 bits 010 300baud...

Page 543: ...eout error AL is preserved Receive Character Receive input a character in AL wait for a character if necessary On exit AH will contain the RS 232 status except that only the error bits 1 2 3 4 7 can b...

Page 544: ...2 parity error Bit3 framingerror Bit4 breakdetect Bit 5 transmitter holding register empty Bit 6 transmitter shift register empty Bit 7 timeout occurred AL modem status as follows set true Bit 0 delt...

Page 545: ...17hex 23 dec Function Summary AH 0 Print character AH 1 Reset printer port AH 2 Get current printer status Function Descriptions Print a Character Entry Conditions AH 0 AL character toprint DX printe...

Page 546: ...status See the following Get Current Printer Status AH 2 Get Current Printer Status Read the printer status into AH Entry Conditions AH 2 Exit Conditions DX AH printer to be used 0 2 printerstatus as...

Page 547: ...setting the multiplexer for audio source is also provided Software Interrupts 1Ahex 26 dec Function Summary AH 0 Get time of day AH 1 Set time of day AH 2 Read real time clock AH 3 Set real time cloc...

Page 548: ...cant portion of the clock count low least significant portion of the clock count 0 of the clock was read or written via AH 0 l within the current 24 hour period otherwise AL 0 Set Time of Day Set writ...

Page 549: ...me of day kept in the clock Entry Conditions AH 2 Exit Conditions CH hoursinBCD CL minutesinBCD DH secondsinBCD Set Clock Time of Day Set the time of day kept in the clock Entry Conditions AH 3 CH hou...

Page 550: ...ate kept in the clock Entry Conditions AH 4 Exit Conditions CH centuryinBCD CL yearinBCD DH monthinBCD DL dayinBCD Set Clock Date Set the date kept in the clock Entry Conditions AH 5 CH centuryinBCD C...

Page 551: ...Soware Sound Multiplexer Sets the multiplexer for audio source Entry Conditions AH AL 00 02 03 80 source of sound 8253channel 2 audio in complex sound generator chip 30...

Page 552: ...c Function Summary AH 0 AH 1 AH 2 AH 3 AH 4 AH 5 AH 08H AH 15H AH 16H Reset diskette Return statusof last diskette operation Read sector s from diskette Write sector s to diskette Verify sector s on d...

Page 553: ...ll diskette drives Entry Conditions AH 0 Exit Conditions See the following ExitsFrom All Calls Return Status of Last Diskette Operation Returns the diskette status of the last operation in AH Entry Co...

Page 554: ...ter to disk buffer drive number 0 2 if Tandy 1000TL 0 1if Tandy 1000SL Exit Conditions See the following Exits from all Calls AL number of sectors read Write Sector s to Diskette Write the desired sec...

Page 555: ...1 CH track number 0 79 CL sector number 1 9 AL sector count 1 9 drive number 0 2if Tandy 1000TL 0 1if Tandy 1000SL Exit Conditions Seethe following Exits From All Calls AL number o f sectors verified...

Page 556: ...024 Exit Conditions See the following Exits From All Calls Read Drive Parameters Return the drive parameters Entry Conditions AH 08H DL drive number 0 2if Tandy 1000TL 0 1 if Tandy 1000SL Exit Conditi...

Page 557: ...AH 15H DL drivenumber 0 1 if Tandy 10000TL 0 1 if Tandy 1000SL Exit Conditions CF 1 Operationwas not successful Previousversions AH 1 Invalid command CF 0 Operation was successful AH 0 Drivenotpresent...

Page 558: ...signal active 80 Diskette drive not ready drive door is open Exits From All Calls AH Error Code Condition 01H IllegalFunction 02H Address Mark Not Found 03H Write Protect Error 04H Sector Not Found 06...

Page 559: ...nt is not in the system Set the indicated equipment is in the system Bit 0 diskette installed Bit 1 math coprocessor Bits 2 3 always 1 1 Bits 4 5 initial video mode 01 40x25 Color 10 80x25 Color 1 1 8...

Page 560: ...us starting from Address 0 in the AX register The maximum value returned is 640 Software Interrupts 12hex 18 dec BootstrapLoader Track 0 Sector 1is read into Segment 0 Offset 7COO Control is then tran...

Page 561: ...000SLand Tandy 1000TL computers have a new BIOS call to further identify the machine All current and previous Tandy 1000 computers have the following machine identification Byte at address FFFF E FF h...

Page 562: ...Tandy 1000 TL Model ID FF FF SubmodelID 00 01 BIOS revision level xx Function Descriptions Read From EEPROM Read the 16 bitvalue from the indicated EEPROM word Entry Conditions AH 70H AL 0 BL word num...

Page 563: ...te to EEPROM Write a 16 bitvalue to the indicated EEPROM word Entry Conditions AH 70H AL 1 BL DX word value to write word number to write 0 63 Exit Conditions Carry Flag set indicates EEPROM call not...

Page 564: ...sound features The API for this new BIOS support is defined in the following information SoftwareInterrupts 1A hex 26 dec Function Summary AH 81H Get sound status AH 82H Input sound from the microphon...

Page 565: ...CF 1 Input Sound Inputs sound from the microphone Entry Conditions AH 82H ES BX bufferaddress CX buffer length DX Exit Conditions Not Busy AH 0 CF 0 Busy AH 0 CF 1 transferrate 1 4095 where 1is the fa...

Page 566: ...rate Stop Sound Input and Output Stops sound input and output Entry Conditions AH 84H Notes The transfer rate values in register DX are not the same for callsAH 82H and AH 83H To input a buffer of da...

Page 567: ...When the DMA transfer is complete the BIOS will receive a hardware interrupt and will execute a software INT 15H with AH 91H and AL FBH If an applica tion program needs to know when the data transfer...

Page 568: ...7 8 38 UP F13 x56 F14 x57 F15 x58 F16 x59 F17 x5A F18 x5B F19 x5c F20 x5D e8700 e8800 PrintScrn Scr Lock Pause X 5 2 e52EO x47 e47EO x49 e47EO X53 e53EO x4F e4FEO x51 e51EO X48 e48EO x4B e4BEO x50 e50...

Page 569: ...t SPACE CapsLock 28 29 5F 28 08 XOF 51 57 45 52 54 59 55 49 4F 50 78 7D OD 41 53 44 4 6 47 48 4A 48 4 c 3A 22 7E 7 c 5A 58 43 56 42 4E 4D 3 c 3E 3F 20 I 7 c us DEL DC1 ETB ENQ DC2 DC4 EM NAK HT SI DLE...

Page 570: ...NT l6H these keys are returned to your program A in the scan code field denotes the extra key on the in ternational version of the enhanced keyboard This key is not available on the standard USA enhan...

Page 571: ...he console A second CPrSchalts printer output Interrupts the current process and allowsanother program to take control if supported When the SysRq key is pressed INT 15H is invoked with AX 8500H When...

Page 572: ...BIOS Data Area MSDOS and BASIC Data Area I O SYS Drivers Available to user Video RAM in 32K video modes Video RAM in 16Kvideo mode Video RAM Window 32K ROM Drive Reserved for system ROM System BIOS R...

Page 573: ...Memory size I O channel RAM size KBD data area Disk data area Video data area Not used Clock data area KBD Break Reset flags Not used Printer timeout counter Comm timeout counter KBD extra data area 0...

Page 574: ...rd 1byte 1byte 1byte current CRT mode 0 7 screen column width byte length of screen address offset of beginning of current display page row col coordinatesof the cursor for each of up to 8 displaypage...

Page 575: ...ws HEX Offset From Segment Length and oo4o oooo Intended Use 3EH 3FH 40H 41H 42H 1byte 1byte 1byte 1byte 7bytes drive recalibration status bit 3 0 if 0 then drive 3 0 needs recalibration before next S...

Page 576: ...n Attempt to DMA Across a 64KBoundary Bad CRC on Disk Read Controller Failure Seek Failure Device Timeout Device Failed to Respond The structure and usage of the RS232 driver RAM data area is as fol l...

Page 577: ...ff 3 ALT key pressed 2 CTRL key pressed 1 Left SHIFT key pressed 0 Right SHIFTkey pressed lbyte Secondary shift state flag Bits INSERT key pressed 6 CAPS LOCK pressed 5 NUM LOCK pressed 4 SCROLL LOCK...

Page 578: ...the clock service routine is as follows HEX Offset From Segment Length and oo4o oooo Intended Use 6CH 6EH 70H 1word 1word 1byte Least significant 16bits of clock count Most significant 16bits of cloc...

Page 579: ...Monochrome monitor B5H 1 byte Bit 0 0 DriveA is 5 1 4 1 Drive A is 3 1 2 Bit 1 0 Drive B is 5 1 4 1 Drive B is 3 1 2 Bit 2 0 Tandy 1000 key board layout 1 IBMkeyboard layout mode mode Bit 4 0 Internal...

Page 580: ...m Segment oo4o oooo Bit 5 0 No external mono chrome video installed 1 Externalmonochromevideo installed B6H 1 byte Bit 0 0 Drive C is 5 1 4 Drive C is 3 1 2 40 C2 1 byte 01 ROM drive is A 02 ROM drive...

Page 581: ...0 Note Note 16 Pause Break E11477 EIF014F077 EllD45 E19DC5 Note 17 o r O E FOOE 2B AB 2960 18 o r 1 16 F016 02 82 0231 0118 5400 5500 5600 5700 5800 5900 5A00 5B00 5c00 5D00 Note Note2 Note3 2978 0221...

Page 582: ...3 0332 04 84 0433 05 85 0534 06 86 0635 07 87 0736 08 88 0837 09 89 0938 OA 8A O A39 OB 8B OB34 OC 8C OC2D OD 8D O D3D OE 8E O E08 E02AE052 EOD2EOAA 5200 E02AE047 EOC7EOAA 4700 E02AE049 EOC9EOAA 4900...

Page 583: ...9A 1A5B 1B 9B 1B5D 2B AB 2B5C E02AE053 EOD3EOAA 5300 E02AE04F EOCFEOAA 4F00 E02AE051 EOD1EOAA 5100 47 c 7 4700 48 C8 4800 49 c 9 4900 OF00 105 I 1 I57 1245 1352 I454 I559 1655 1749 184F 1950 1A7B 1B7...

Page 584: ...9C CB cc CD 4E2B Note 1E61 IF73 2064 2166 2267 2368 246A 256B 266C 273B 2827 ICOD 4B00 4D00 1 E41 I F53 2044 2146 2247 2348 244A 254B 264C 273A 2822 lCOD 4B34 4c35 4D36 _ 1EOl 1F13 2004 2106 2207 2308...

Page 585: ...C8E0AA CF DO D1 9D B8 Note8 2C7A 2D78 2E63 2F76 3062 316E 326D 332C 3428 352F Note8 4800 4F00 5000 5100 Note9 Note Note8 2C5A 2D58 2E43 2F56 3042 314E 3241 333c 3438 353F Note 4800 4F31 5032 5133 Note...

Page 586: ...e Break Scancode ASCII code C a d e C L o d c Norm Shift ClrI Alt Extended ASCII Scancodc ASCII code Norm Sbft __CtrI Ab 10 E038 EOB8 Notcl Notel Note Notc1 Note Note1 Notc9 EOID E09D Note Note9 Notc...

Page 587: ...ted Note4 1NT 1BH is invoked Note5 the numlock active bit is toggled Note6 ALT num pad generates raw ascii code of typed number Note7 the caps lock active bit is toggled Note8 old shift lock active un...

Page 588: ......

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Tandy 1000 SL, Technical Reference Manual

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