1
2
3
4
5
6
A
8
A 3
memory
M
EMORY
L1 cache
(in CPU):
16KB code + 16KB data
L2 cache
:
512KB Pipeline Burst SRAM
RAM (base)
:
0MB EDO (3.3V)
RAM (expansion)*
:
128MB maximum using one or both sockets
Socket 1 & Socket 2 requirements:
16MB, 32MB or 64MB modules
144 pins
3.3-volt
TSOP package
EDO or SDRAM DIMMs
Rated at 60ns or faster
Small outline
*
User upgradable.