EDM1-IMX6 HARDWARE MANUAL
– VER 1.00 – NOV 14 2019
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3.2. LVDS Interface
The EDM1-IMX6 is equipped with single LVDS Display interfaces. The LVDS Display Bridge (LDB)
connects the IPU (Image Processing Unit) to an External LVDS Display Interface. The purpose of the
LDB is to support flow of synchronous RGB data from the IPU to external display devices through LVDS
interface.
The LDB output complies with the EIA-644-A standard and supports the following features:
•
Connectivity to relevant devices - Displays with LVDS receivers.
•
Arranging the data as required by the external display receiver and by LVDS display standards.
•
Synchronization and control capabilities.
•
Data input interface (inside the i.MX6 processor)
o
RGB Data of 18 or 24 bits
o
Pixel clock
o
Control signals: HSYNC, VSYNC, DE, and 1 additional optional general purpose control
(I
2
C)
•
Single channel output data output interface
o
Total of up to 28 bits per data interface are transferred per pixel clock cycle.
•
Data Rates
o
Overall: LDB supports rates needed by WUXGA 16:10 aspect ratio (1920 x 1200 @ 60
frames per second, data rate supported up to 170 MHz)
o
For single input data interface case: Up to 170 MHz pixel clock (WUXGA 1920x1200)
o
For dual input data interface case: Up to 85 MHz per interface. (WXGA 1366x768 @ 60
frames per second, 35% blanking).
For additional details, please refer to
the “LVDS Display Bridge (LDB)” chapter of the “i.MX6 Reference
Manual”.
