TAM-3517 HARDWARE MANUAL rev B
July 3 2012, TechNexion
14
5.3
Memory
5.3.1
Hynix H5PS1G63EFR (option 1)
The TAM-3517 has a single channel 32 bit External Memory Interfaces (EMI) controller.
The 32 bit wide channel is connected 16 bit wide to two Hynix H5PS1G63EFR DDR2 SDRAM
Chips. The SDRAM_nCS0 signal is used to select them.
The standard configuration is organized as
1Gbit (4Bank x 16M x 16bits). Therefore given 2
chips are used a total of 2Gbit or 256MB of memory is available.
Features:
VDD = 1.8 +/- 0.1V
VDDQ = 1.8 +/- 0.1V
All inputs and outputs are compatible with SSTL_18 interface
8 banks
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
Differential Data Strobe (DQS, DQS)
Data outputs on DQS, DQS edges when read (edged DQ)
Data inputs on DQS centers when write(centered DQ)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM mask write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on
the rising edges of the clock
Programmable CAS latency 3,4, 5, 6 and 7 supported
Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
Programmable burst length 4/8 with both nibble sequential and interleave mode
Internal eight bank operations with single pulsed RAS
Auto refresh and self refresh supported
tRAS lockout supported
8K refresh cycles /64ms
JEDEC standard 84ball FBGA(x16)
Full strength driver option controlled by EMR
On Die Termination supported
Off Chip Driver Impedance Adjustment supported
Read Data Strobe supported (x8 only)
Self-Refresh High Temperature Entry
Average Refresh Period 7.8us at lower than Tcase 85°C, 3.9us at 85°C<Tcase<95°C
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