TAM-3517 HARDWARE MANUAL rev B
July 3 2012, TechNexion
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5.3.2
Micron MT47H64M16 (option 2)
The TAM-3517 has a single channel 32 bit External Memory Interfaces (EMI) controller.
The 32 bit wide channel is connected 16 bit wide to two Micron MT47H64M16 DDR2 SDRAM
Chips. The SDRAM_nCS0 signal is used to select them.
The standard configuration is organized as
1Gbit (8M x 16bits x 8 banks). Therefore, given 2
chips are used; a total of 2Gbit or 256MB of memory is available.
Features:
VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4
n
-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1 tCK
Selectable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
On-die termination (ODT)
Industrial temperature (IT) option
RoHS-compliant
Supports JEDEC clock jitter specification
This memory is compatible with the Hynix memory and uses the same software.
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