TAM-3517 HARDWARE MANUAL rev B
July 3 2012, TechNexion
16
5.3.3
Nanya NT5TU64M16GG (option 3)
The TAM-3517 has a single channel 32 bit External Memory Interfaces (EMI) controller.
The 32 bit wide channel is connected 16 bit wide to two Nanya NT5TU64M16GG DDR2
SDRAM Chips. The SDRAM_nCS0 signal is used to select them.
The standard configuration is organized as
1Gbit (8M x 16bits x 8 banks). Therefore, given 2
chips are used; a total of 2Gbit or 256MB of memory is available.
Features:
1.8V ± 0.1V Power Supply Voltage
8 internal memory banks
Programmable CAS Latency: 3, 4, 5 (DDR2-3C/-3CI/-AC/-ACI/-ACL), 6 (-BD), 7 (-BE)
Programmable Additive Latency: 0, 1, 2, 3, 4 5
Write Latency = Read Latency -1
Programmable Burst Length:
4 and 8 Programmable Sequential / Interleave Burst
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
4n-bit prefetch architecture
Data-Strobes: Bidirectional, Differential
Support Industrial grade temperature -40
℃
~95, Operating Temperature (-3CI/-ACI)
2KB page size for x16
Strong and Weak Strength Data-Output Driver
Auto-Refresh and Self-Refresh
Power Saving Power-Down modes
7.8 μs max. Average Periodic Refresh Interval
RoHS Compliance
Packages:
84-Ball BGA for x16 components
This memory is compatible with the Hynix memory and uses the same software.
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