TAM-3517 HARDWARE MANUAL rev B
July 3 2012, TechNexion
18
5.4.2
MT29F2G16ABDHC-ET
NAND on the TAM-3517 is populated as Micron MT29F2G16ABDHC and connected 16 bit wide
to the AM3517 GPMC bus.
The TAM-3517 supports the chip which provides 256MB of addressable space.
The GPMC_nCS0 signal is used for its selection.
Features:
• Open NAND Flash Interface (ONFI) 1.0-compliant
• Single-level cell (SLC) technology
• Organization
Page size:
• x8: 2,112 bytes (2,048 + 64 bytes)
• x16: 1,056 words (1,024 + 32 words)
Block size: 64 pages (128K + 4K bytes)
Device size: 2Gb: 2,048 blocks
• READ performance
Random READ: 25μs
Sequential READ: 25ns (3.3V)
Sequential READ: 35ns (1.8V)
• WRITE performance
PROGRAM PAGE: 220μs (TYP, 3.3V)
PROGRAM PAGE: 300μs (TYP, 1.8V)
BLOCK ERASE:
500μs (TYP)
• Data retention: 10 years
• Endurance: 100,000 PROGRAM/ERASE cycles
• First block (block address 00h) guaranteed to be valid with ECC when shipped from factory
• Industry-standard basic NAND Flash command set
• Advanced command set:
PROGRAM PAGE CACHE MODE
PAGE READ CACHE MODE
One-time programmable (OTP) commands
BLOCK LOCK (1.8V only)
PROGRAMMABLE DRIVE STRENGTH
READ UNIQUE ID
• Operation status byte provides a software method of detecting:
Operation completion
Pass/fail condition
Write-protect status
• Ready/busy# (R/B#) signal provides a hardware method of detecting operation completion
• WP# signal: write protect entire device
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