TAM-3517 HARDWARE MANUAL rev B
July 3 2012, TechNexion
43
8.2
Video Interfaces –CAM Signals description
SIGNAL NAME
DESCRIPTION
TYPE PIN TAM-3517
CCDC_HD
Camera Horizontal Synchronization
IO
46
CCDC _VD
Camera Vertical Synchronization
IO
48
CCDC _data0
Camera digital image data bit 0
I
50
CCDC _data1
Camera digital image data bit 1
I
51
CCDC _data2
Camera digital image data bit 2
I
56
CCDC _data3
Camera digital image data bit 3
I
53
CCDC _data4
Camera digital image data bit 4
I
52
CCDC _data5
Camera digital image data bit 5
I
54
CCDC _data6
Camera digital image data bit 6
I
57
CCDC _data7
Camera digital image data bit 7
I
55
CCDC _fld
Camera field identification
IO
49
CCDC _pclk
Camera pixel clock
I
42
CCDC _wen
Camera Write Enable
I
44
The video processing subsystem (VPSS) includes a video processing front-end (VPFE)
controller, which is the video input portion of the processor. The VPFE controller receives input
video/image data from external capture devices and stores it to external memory. A built-in DMA
engine transfers the capture data into the external memory. An internal buffer block provides a
high bandwidth path between the VPSS module and the external memory. The CPU, Cortex-A8,
will process the image data based on application requirements.
The VPFE controller supports the following features:
It supports conventional Bayer pattern and Foveon sensor formats.
It is flexible in synchronization timing generation. It can be programmed to synchronize
to the external horizontal/vertical sync and field ID signals with various timings.
It supports progressive and interlaced sensors (hardware support for up to two fields and
firmware support for a higher number of fields, typically 3, 4, and 5-field sensors).
The max pixel clock is 75 MHz.
It supports the REC656/CCIR-656 standard.
It supports YCbCr 422 format, 8-bit with discrete horizontal and vertical sync signals.
The input capture data can be up to 8 bits.
It can generate optical black clamping signals.
It has built-in digital clamping and black level compensation.
8-bit A-law compression hardware is provided.
It has a low-pass filter that can be applied prior to writing the capture data to external
memory. If this filter is enabled, two pixels in each the left and the right edges of each
line are cropped from the output.
The output data is 8 bits wide.
It has a programmable culling block that can perform down-sampling of the input data.
An external write enable signal is provided to control the timing of outputting data to the
external memory.
It supports up to 16K pixels (image size) in both the horizontal and vertical directions.
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