TEK-CPCI-1003 Technical Reference Manual
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Supported Processors
Single 233MHz, 266MHz, or 300MHz Mobile Pentium II processor with Intel’s
82443BX and 82371AB PIIX4 chipset.
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Memory
System memory
:
The TEK-CPCI-1003 supports from 8MB to 384MB vertical
SDRAM on three 168-pin DIMMs sockets with ECC
capabilities. Registered SDRAM (RSDRAM) is also
supported for up to 768MB of system memory.
Internal cache
:
32KB (L1), 512KB (L2) pipelined burst cache is implemented
to enhance the processor operations by eliminating wait states
on cache accesses.
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CompactPCI Connectors
Rear panel CPCI connectors are PICMG 2.0 R2.1 CompactPCI
specification
compliant. CompactPCI connectors are located at the rear edge of the board. The
complete CPCI connector configuration is composed of five connectors referred to as
J1, J2, J3, J4, and J5. They are defined as 2mm pitch, shielded connectors with a 5x47
array of pin for signals and 2 rows of 47 pins for shielding.
Their function is described below:
J1/J2:
carry out arbitration and PCI bus signals, and power.
J3/J4/J5: handle I/O signals.
Summary of Contents for TEK-CPCI 1003
Page 15: ...TEK CPCI 1003 Technical Reference Manual 5 4 5 1 CONNECTOR LOCATION...
Page 22: ...FEATURE DESCRIPTION 7 ONBOARD FEATURES...
Page 51: ...TEK CPCI 1003 Technical Reference Manual 9 2 JUMPER LOCATION...
Page 52: ...Setting Jumpers 9 3 JUMPER SETTINGS Table 1...
Page 53: ...TEK CPCI 1003 Technical Reference Manual 9 4 JUMPER SETTINGS TABLE 2...
Page 67: ...SOFTWARE SETUPS 12 AWARD SETUP PROGRAM 13 UPDATING THE BIOS WITH UPGBIOS 14 VT100 MODE...
Page 95: ...C 1 C BOARD DIAGRAMS C 1 ASSEMBLY TOP DIAGRAM...