Post Codes & Error Codes F-5
POST
DESCRIPTION
CODE
50
Memory testing/initialization below 1M complete.
Going to adjust displayed memory size for relocation/ shadow.
51
Memory size display adjusted due to relocation/ shadow.
Memory test above 1M to follow.
52
Memory testing/initialization above 1M complete.
Going to save memory size information.
53
Memory size information is saved. CPU registers are saved.
Going to enter in real mode.
54
Shutdown successful, CPU in real mode. Going to disable
gate A20 line and disable parity/NMI.
57
A20 address line, parity/NMI disable successful.
Going to adjust memory size depending on relocation/shadow.
58
Memory size adjusted for relocation/shadow.
Going to clear Hit <DEL> message.
59
Hit <DEL> message cleared. <WAIT...> message displayed.
About to start DMA and interrupt controller test.
60
DMA page register test passed. To do DMA#1 base register test.
62
DMA#1 base register test passed. To do DMA#2 base register test.
65
DMA#2 base register test passed. To program DMA unit 1 and 2.
66
DMA unit 1 and 2 programming over.
To initialize 8259 interrupt controller.
7F
Extended NMI sources enabling is in progress.
80
Keyboard test started. clearing output buffer, checking for stuck key,
to issue Keyboard reset command.
81
Keyboard reset error/stuck key found. To issue Keyboard controller
interface test command.
82
Keyboard controller interface test over. To write command byte and init
circular buffer.
83
Command byte written, Global data init done. To check for lock-key.
84
Lock-key checking over. To check for memory size mismatch with
CMOS.
85
Memory size check done. To display soft error and check for password or
bypass setup.
86
Password checked. About to do programming before setup.
87
Programming before setup complete. To uncompress SETUP code and
execute CMOS setup.
Summary of Contents for VIPer808
Page 21: ...Installing Memory 2 3 DIAGRAM 2 1 Assembly Top...
Page 22: ...Installing Memory 2 5 DIAGRAM 2 2 Assembly Bottom...
Page 26: ...Setting Jumpers 3 3 DIAGRAM 3 1 VIPer808 Jumper Locations with Default Settings...
Page 28: ...Setting Jumpers 3 6 TABLE 3 1a Jumper Settings W1 W4 W13 W14...
Page 29: ...Setting Jumpers 3 7 TABLE 3 1b AMD DX2 DX4 CPU Jumper Settings W1 W15 W15C...
Page 30: ...Setting Jumpers 3 8 TABLE 3 1c AMD 5x86 CPU Jumper Settings W1 W15 W15C...
Page 31: ...Setting Jumpers 3 9 TABLE 3 1d Intel CPU Jumper Settings W1 W15 W15C...
Page 32: ...Setting Jumpers 3 10 TABLE 3 1e SGS CPU Jumper Settings W1 W15 W15C...
Page 33: ...Setting Jumpers 3 11 TABLE 3 1f Jumper Settings W18 W20 W23...
Page 92: ...Memory I O Maps B 1 APPENDIX B MEMORY I O MAPS B 01 MEMORY MAPS DIAGRAM B 1 Memory Map Diagram...
Page 96: ...Mechanical Layout Block Diagram C 3 DIAGRAM C 1 Mechanical Specifications...
