Theory
of
Operation—
DM 5010
5. The source,
upon sensing the high NRFD level, sets
the
DAV level to a low, indicating that the data on the DIO
lines has
settled
and is valid.
6. The first (fastest) acceptor sets the NRFD level low,
indicating
that it is no longer ready for new data, and ac
cepts the
present data. The remaining acceptors follow at
their own rates.
7. The first acceptor sets its NDAC level to a (passive)
high, indicating that
it has accepted the data. (NDAC re
mains low due to the other acceptors actively driving NDAC
low. The term
“passive" means that if any other device is
“
actively" driving this line to the opposite state, the passive
level is overridden.)
8. As the last (slowest) acceptor accepts the present
data, the NDAC level
goes to a
(passive) high, indicating
that
all
acceptors
have accepted the data.
9. The source, having sensed the high NDAC level, sets
DAV high. This indicates to the acceptors that the data on
the
DIO lines must now
be considered invalid.
16.
The first acceptor sets its NDAC level to a (passive)
high,
indicating that it has accepted the data (as in step 7
above).
17.
The last
acceptor sets
the NDAC level (passive)
high,
indicating that it has accepted the data (as in step 8
above).
18. The source, having sensed that NDAC is high,
sets
DAV high (as in 9).
19.
The source
removes the data byte from the DIO sig
nal lines after setting
DAV high.
20.
The acceptors, upon sensing the
high DAV
level, set
NDAC
to a low level
in preparation for the next cycle.
21.
Note that
all three
handshake
lines are at their
initial
states
(as in
steps 1
and 2 above).
10.
The source may change the data on the DIO lines at
this
time, and
now
delays to allow this data to settle
if
changed.
11. The
acceptors, upon sensing the high DAV level
(step
9, above),
set the NDAC level low in preparation for
the
next cycle. The NDAC line
goes low when set by the first
acceptor.
12.
The first
acceptor indicates that it is now ready
for
the next data byte by setting its NRFD level to a (passive)
high. (NRFD remains low
due to other acceptors actively
driving
it
low.)
13.
When the last
acceptor indicates that it is ready
for
the
next data
byte,
the NRFD level goes (passive) high.
14.
The source, sensing that NRFD
is high, sets the
DAV
level
low, indicating
that the new data on the DIO lines
has
settled and is valid.
15. The first acceptor sets the NRFD level low,
indicat
ing that it is not ready to accept any change of data, then
accepts
the present
data. The other acceptors follow at
their own rate.
GPIB
Interface
The purpose of the GPIB
Interface is to provide interface
between
the
IEEE 488-1978 Standard bus
and the DM 5010
microprocessor.
The DM 5010 GPIB
Interface consists pri
marily of a 40-pin IC designed
specifically for GPIB applica
tions and two bidirectional current buffer ICs.
On the bus
side of the GPIB IC, U1105,16 pins are relat
ed
directly
to the 16 signal lines defined in the IEEE 488-
1978 Standard
description
above. These data, control,
and
handshake signals
are buffered
by
U1100 and U1110 either
from
U1105
to the GPIB or vice versa, depending on the
T/R (Transmit-Receive) direction control
signal. This T/R is
also
inverted by Q1121 and is provided to the TM 5000-
Series
power module
for future use.
The GPIB IC is
a
register-oriented device; i.e.,
its function
depends
on how its
various internal registers have been set.
The
various control and addressing
signals that determine
the
setting of these registers
are applied to the micro
processor
side
of
the IC.
At
power
up, the negative PON pulse sets all internal
registers
of the GPIB IC to predefined states. When the
Address Decode circuitry detects
that a GPIB function is to
be
performed,
it sets EGPIB (Enable GPIB) low and the
GPIB IC is enabled.
4-28
ADD
JAN 1982
Summary of Contents for DM 5010
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